View E713607_982556.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

To Top / Lineup / Index
FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13607-3E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90650A Series
MB90652A/653A/P653A/654A/F654A
s DESCRIPTION
The MB90650A series are 16-bit microcontrollers designed for high speed real-time processing in consumer product applications such as controlling celluar phones, CD-ROMs, or VTRs. Based on the F2MC*1-16L CPU core, an F2MC-16L is used as the CPU. This CPU includes high-level language-support instructions and robust task switching instructions, and additional addressing modes. In order to reduce the consumption current, dualclock (main/sub) is used. Furthermore, low consumption power supply is achieved by using stop mode, sleep mode, watch mode, pseudo-watch mode, CPU intermittent operation mode. Microcontrollers in this series have built-in peripheral resources including 10-bit A/D converter, 8-bit D/A converter, UART, 8/16-bit PPG, 8/16-bit up/down counter/timer, I2C interface*2, 8/16-bit I/O timer (input capture, output compare, and 16-bit free-run timer). *1:F2MC stands for FUJITSU Flexible Microcontroller. *2:Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
s FEATURES
F2MC-16L CPU * Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4 * Instruction set optimized for controller applications Object code compatibility with F2MC-16(H)
(Continued)
s PACKAGE
100-pin plastic LQFP 100-pin plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
To Top / Lineup / Index
MB90650A Series
(Continued) Wide range of data types (bit, byte, word, and long word) Improved instruction cycles provide increased speed Additional addressing modes: 23 modes High code efficiency Access methods (bank access, linear pointer) High precision operations are enhanced by use of a 32-bit accumulator Extended intelligent I/O service (access area extended to 64 Kbytes) Maximum memory space: 16 Mbytes * Enhanced high level language (C) and multitasking support instructions Use of a system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Improved execution speed: Four byte instruction queue * Powerful interrupt function * Automatic data transfer function that does not use instruction (extended I2OS)
2
To Top / Lineup / Index
MB90650A Series
s PRODUCT LINEUP
Part number MB90652A Item
Classification ROM size RAM size Power supply voltage CPU functions Mask ROM product 64 Kbytes 3 Kbytes 2.2 V to 3.6 V The number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: I/O ports (N-channel open-drain): I/O ports (CMOS): OTPROM product For evaluation 128 Kbytes 5 Kbytes 2.7 V to 5.5 V -- Mask ROM FLASH product product 256 Kbytes
MB90653A
MB90P653A
MB90V650A
MB90654A
MB90F654A
8 Kbytes
2.2 V to 3.6 V 2.4 V to 3.6 V
Ports
A/D converter
D/A converter 8/16-bit up/down counter/timer I2C interface UART
I/O extended serial interface 8/16-bit PPG 16-bit I/O timer DTP/external interrupt Timer functions DTMF generator Low-power consumption modes PLL function Other
340 8/16 bits 1 to 7 bytes 1/4/8/16/32 bits 62.5 ns/4 MHz (PLL multiplier = 4) 1.0 s/16 MHz (minimum) 4 75 (Input pull-up resistors available: 24/ Can be set as N-channel open-drain: 8) Total: 79 Analog inputs : 8 channels Analog inputs: 8 channels Analog inputs : 8 channels 10-bit resolution 10-bit resolution 10-bit resolution Conversion time : minimum Conversion time : minimum 12.25 Conversion time : minimum s/8 MHz 6.13 s/16 MHz 6.13 s/16 MHz 2 channels (independent), 8-bit resolution, R-2R type 16 bits x 1 channel/8 bits x 2 channels selectable Includes reload and compare functions. 1 channel Master mode/slave mode available 1 channel Clock synchronous communication Clock asynchronous communication 8 bits x 2 channels LSB-first or MSB-first operation selecable 8 bits x 2 channels/16 bits x 1 channel selectable 1 channel (Input capture x 2 channels, output compare x 4 channels, and free-run timer x 1 channel) 8 inputs Timebase timer (18-bit)/watchdog timer (18-bit)/watch timer (15-bit) Supports every ITU-T (CCITT) tone for output (Internal 16 MHz shall be used for DTMF generator). CPU intermittent operation mode, sub clock mode, stop mode, sleep mode, watch mode, pseudo-watch mode Selectable multiplier: 1/2/3/4 (Set a multiplier that does not exceed the assured operation frequency range.) VPP is shared with the MD2 pin -- -- (for EPROM programming) FPT-100P-M05, FPT-100P-M06 PGA-256C-A02 FPT-100P-M05, FPT-100P-M06
Package
Notes: * MB90V650A device is assured only when operate with the tools, under the condition of power supply voltage: 2.7 V to 3.3 V, operating temparature: 0C to 70C and operating frequency: 1.5 MHz to 8MHz * For more information about each package, see seciton "PACKAGE DIMENSIONS". 3
To Top / Lineup / Index
MB90650A Series
s PIN ASSIGNMENT
(Top view)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P21/A17 P20/A16 P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC1 X1 X0 VSS X0A X1A PA2/OUT2
4
P71/SCL P72 DVRH DVSS P73/DA00 P74/DA01 AVCC AVRH AVRL AVSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 VSS P54/AN4 P55/AN5 P56/AN6 P57/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 TEST
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 VCC2 P45/SCK1 P46/ADTG P47 P70/SDA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RST PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/ZIN1 P94/BIN1 P93/AIN1/IRQ7 P92/ZIN0 P91/BIN0 P90/AIN0/IRQ6 P67/PPG11 P66/PPG10 P65/CKOT P64/PPG01 P63/PPG00 P62/SCK2 P61/SOT2 P60/SIN2 DTMF P86/OUT3 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2
(FPT-100P-M05)
To Top / Lineup / Index
MB90650A Series
(Top view)
DVSS P73/DA00 P74/DA01 AVCC AVRH AVRL AVSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 VSS P54/AN4 P55/AN5 P56/AN6 P57/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 VCC2 P45/SCK1 P46/ADTG P47 P70/SDA P71/SCL P72 DVRH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC1 X1 X0 VSS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
X0A X1A PA2/OUT2 RST PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/ZIN1 P94/BIN1 P93/AIN1/IRQ7 P92/ZIN0 P91/BIN0 P90/AIN0/IRQ6 P67/PPG11 P66/PPG10 P65/CKOT P64/PPG01 P63/PPG00 P62/SCK2 P61/SOT2 P60/SIN2 DTMF P86/OUT3 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 TEST MD2
(FPT-100P-M06)
5
To Top / Lineup / Index
MB90650A Series
s PIN DESCRIPTION
Pin no. LQFP*1 80 81 77 78 47 to 49 50 75 83 to 90 QFP*2 82 83 79 80 49 to 51 52 77 85 to 92 Pin name X0 X1 X1A X0A MD0 to MD2 TEST RST P00 to P07 Circuit type A A B B D D C Crystal oscillator pin Crystal oscillator pin Crystal oscillatort pins (32 kHz) Crystal oscillatort pins (32 kHz) Operating mode selection pins Connect directly to VCC or VSS. Test input pin This pin must always be fixed to "H". Reset input pin Function
E General-purpose I/O ports (STBC) Pull-up resistors can be set (RD07 to RD00 = "1") using the pull-up resistor setting register (RDR0). The setting does not apply for ports set as outputs (D07 to D00 = "1": invalid at the output setting). In external bus mode, the pins function as the lower data I/O or lower address outputs (AD00 to AD07). E General-purpose I/O ports (STBC) Pull-up resistors can be set (RD17 to RD10 = "1") using the pull-up resistor setting register (RDR1). The setting does not apply for ports set as outputs (D17 to D10 = "1": invalid at the output setting). In 16-bit external bus mode, the pins function as the upper data I/O or middle address outputs (AD08 to AD15). I General-purpose I/O ports (STBC) In external bus mode, pins for which the corresponding bit in the HACR register is "0" function as the P20 to P27 pins. In external bus mode, pins for which the corresponding bit in the HACR register is "1" function as the upper address output pins (A16 to A23). I General-purpose I/O port (STBC) Functions as the ALE pin in external bus mode. Functions as the address latch enable signal. I General-purpose I/O port (STBC) Functions as the RD pin in external bus mode. Functions as the read strobe output (RD). I General-purpose I/O port (STBC) Functions as the WRL pin in external bus mode if the WRE bit in the ECSR register is "1". Functions as the lower data write strobe output (WRL).
AD00 to AD07 91 to 98 93 to 100 P10 to P17
AD08 to AD15 99, 100, 1 to 6 1, 2, 3 to 8 P20, P21, P22 to P27 A16, A17, A18 to A23 7 9 P30 ALE 8 10 P31 RD 10 12 P32
WRL *1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
6
To Top / Lineup / Index
MB90650A Series
Pin no. LQFP*1 11 QFP*2 13
Pin name P33
Circuit type
Function
I General-purpose I/O port (STBC) Functions as the WRH pin in 16-bit external bus mode if the WRE bit in the ECSR register is "1". Functions as the upper data write strobe output (WRH). I General-purpose I/O port (STBC) Functions as the HRQ pin in external bus mode if the HDE bit in the ECSR register is "1". Functions as the hold request input pin (HRQ). I General-purpose I/O port (STBC) Functions as the HAK pin in external bus mode if the HDE bit in the ECSR register is "1". Functions as the hold acknowledge output (HAK) pin. I General-purpose I/O port (STBC) Functions as the RDY pin in external bus mode if the RYE bit in the ECSR register is "1". Functions as the external ready input (RDY) pin. I General-purpose I/O port (STBC) Functions as the CLK pin in external bus mode if the CKE bit in the ECSR register is "1". Functions as the machine cycle clock output (CLK) pin. H General-purpose I/O port (STBC) When UART0 is operating, the data at the pin is used as the serial input (SIN0). Can be set as an open-drain output port (OD40 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D40 = "0": invalid at the input setting). Functions as the UART0 serial input (SIN0). G General-purpose I/O port (STBC) Functions as the SOT0 pin if the SOE bit in the UMC register is "1". Can be set as an open-drain output port (OD41 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D41 = "0": invalid at the input setting). Functions as the UART0 serial data output pin (SOT0).
WRH 12 14 P34
HRQ 13 15 P35
HAK 14 16 P36
RDY 15 17 P37
CLK 16 18 P40
SIN0 17 19 P41
SOT0 *1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
7
To Top / Lineup / Index
MB90650A Series
Pin no. LQFP*1 18 QFP*2 20
Pin name P42
Circuit type
Function
H General-purpose I/O port (STBC) When UART0 is operating in external shift clock mode, the data at the pin is used as the clock input (SCK0). Also, functions as the SCK0 pin if the SOE bit in the UMC register is "1". Can be set as an open-drain output port (OD42 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D42 = "0": invalid at the input setting). Functions as the UART0 serial clock I/O pin (SCK0). H General-purpose I/O port (STBC) When I/O extended serial is operating, the data at the pin is used as the serial input (SIN1). Can be set as an open-drain output port (OD43 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D43 = "0": invalid at the input setting). Functions as the serial input for I/O extended serial data. G General-purpose I/O port (STBC) Functions as the SOT1 pin if the SOE bit in the UMC register is "1". Can be set as an open-drain output port (OD44 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D44 = "0": invalid at the input setting). Functions as the output pin (SOT1) for I/O extended serial data. H General-purpose I/O port (STBC) When I/O extended serial is operating in external shift clock mode, the data at the pin is used as the clock input (SCK1). Also, functions as the SCK1 pin if the SOE bit in the UMC register is "1". Can be set as an open-drain output port (OD45 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D45 = "0": invalid at the input setting). Functions as the I/O extended serial clock I/O pin (SCK1). G General-purpose I/O port (STBC) Can be set as an open-drain output port (OD46 = "1") by the open-drain control register (ODR4). The setting does not apply for ports set as inputs (D46 = "0": invalid at the input setting). Functions as the external trigger input pin for the A/D converter. K
(NMOS/H)
SCK0 19 21 P43
SIN1 20 22 P44
SOT1 22 24 P45
SCK1 23 25 P46
ADTG 24 26 P47
Open-drain type general-purpose I/O port
(STBC) *1: FPT-100P-M05 *2: FPT-100P-M06 8
(Continued)
To Top / Lineup / Index
MB90650A Series
Pin no. LQFP*1 36 to 39, 41 to 44 QFP*2
Pin name
Circuit type L General-purpose I/O ports (STBC)
Function
38 to 41, P50 to P53, 43 to 46 P54 to P57 AN0 to AN3, AN4 to AN7
The pins are used as analog inputs (AN0 to AN7) when the A/D converter is operating. F General-purpose I/O port (STBC) A pull-up resistor can be set (RD60 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D60 = "1": invalid at the output setting). Functions as a data input pin (SIN2) for I/O extended serial. E General-purpose I/O port (STBC) Function as the SOT2 pin if the SOE bit in the UMC register is "1". A pull-up resistor can be set (RD61 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D61 = "1": invalid at the output setting). Functions as an output pin (SOT2) for I/O extended serial data. F General-purpose I/O port (STBC) When I/O extended serial is operating in external shift clock mode, the data at the pin is used as the clock input (SCK2). Also, functions as the SCK2 pin if the SOE bit in the UMC register is "1". A pull-up resistor can be set (RD62 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D62 = "1": invalid at the output setting). Functions as the I/O extended serial clock I/O pin (SCK2). E General-purpose I/O port (STBC) A pull-up resistor can be set (RD63 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D63 = "1": invalid at the output setting). Functions as the PPG00 output when PPG output is enabled. E General-purpose I/O port (STBC) A pull-up resistor can be set (RD64 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D64 = "1": invalid at the output setting). Functions as the PPG01 output when PPG output is enabled.
57
59
P60
SIN2 58 60 P61
SOT2 59 61 P62
SCK2 60 62 P63
PPG00 61 63 P64
PPG01 *1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
9
To Top / Lineup / Index
MB90650A Series
Pin no. LQFP*1 62 QFP*2 64
Pin name P65
Circuit type
Function
E General-purpose I/O port (STBC) A pull-up resistor can be set (RD65 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D65 = "1": invalid at the output setting). Functions as the CKOT output when CKOT is operating. E General-purpose I/O port (STBC) A pull-up resistor can be set (RD66 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D66 = "1": invalid at the output setting). Functions as the PPG10 output when PPG output is enabled. E General-purpose I/O port (STBC) A pull-up resistor can be set (RD67 = "1") using the pull-up resistor setting register (RDR6). The setting does not apply for ports set as outputs (D67 = "1": invalid at the output setting). Functions as the PPG11 output when PPG output is enabled. K
(NMOS/H)
CKOT 63 65 P66
PPG10 64 66 P67
PPG11 25 27 P70 SDA
Open-drain type I/O port
2 (STBC) I C interface data I/O pin This function is valid when I2C interface operations are enabled. Set port output to Hi-Z (PDR = 1) during I2C interface operations.
26
28
P71 SCL
K
(NMOS/H)
Open-drain type I/O port
2 (STBC) I C interface clock I/O pin This function is valid when I2C interface operations are enabled. Set port output to Hi-Z (PDR = 1) during I2C interface operations.
27 30
29 32
P72 P73
K Open-drain type I/O port (STBC) M Open-drain type I/O port (STBC) Functions as a D/A output pin when DAE0 = "1" in the D/A control register (DACR). Functions as D/A output 0 when the D/A converter is operating. M General-purpose I/O port (STBC) Functions as a D/A output pin when DAE1 = "1" in the D/A control register (DACR). Functions as D/A output 1 when the D/A converter is operating. J General-purpose I/O port Functions as external interrupt request I/O 0.
DA00 31 33 P74
DA01 45 47 P80 IRQ0 *1: FPT-100P-M05 *2: FPT-100P-M06 10
(Continued)
To Top / Lineup / Index
MB90650A Series
Pin no. LQFP*1 46 51 52 53 54 55 QFP*2 48 53 54 55 56 57
Pin name P81 IRQ1 P82 IRQ2 P83 IRQ3 P84 IRQ4 P85 IRQ5 P86 OUT3
Circuit type J J J J J General-purpose I/O port
Function
Functions as external interrupt request I/O 1. General-purpose I/O port Functions as external interrupt request I/O 2. General-purpose I/O port Functions as external interrupt request I/O 3. General-purpose I/O port Functions as external interrupt request I/O 4. General-purpose I/O port Functions as external interrupt request I/O 5. I General-purpose I/O port (STBC) This applies in all cases. Event output for channel 3 of the output compare J General-purpose I/O port Input to channel 0 of the 8/16-bit up/down counter/timer Functions as an interrupt request input. General-purpose I/O port J (STBC) Input to channel 0 of the 8/16-bit up/down counter/timer J General-purpose I/O port (STBC) Input to channel 0 of the 8/16-bit up/down counter/timer J General-purpose I/O port Input to channel 1 of the 8/16-bit up/down counter/timer Functions as an interrupt request input. J General-purpose I/O port (STBC) Input to channel 1 of the 8/16-bit up/down counter/timer J General-purpose I/O port (STBC) Input to channel 1 of the 8/16-bit up/down counter/timer J General-purpose I/O port (STBC) Trigger input for channel 0 of the input capture J General-purpose I/O port (STBC) Trigger input for channel 1 of the input capture I General-purpose I/O port (STBC) Event output for channel 0 of the output compare
65
67
P90 AIN0 IRQ6
66 67 68
68 69 70
P91 BIN0 P92 ZIN0 P93 AIN1 IRQ7
69 70 71 72 73
71 72 73 74 75
P94 BIN1 P95 ZIN1 P96 IN0 P97 IN1 PA0 OUT0
*1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
11
To Top / Lineup / Index
MB90650A Series
(Continued)
Pin no. LQFP*1 74 76 82 21 9, 40, 79 32 33 34 35 28 29 56 QFP*2 76 78 84 23 11, 42, 81 34 35 36 37 30 31 58 Pin name PA1 OUT1 PA2 OUT2 VCC1 VCC2 VSS -- AVCC AVRH AVRL AVSS DVRH DVSS DTMF -- -- -- -- -- -- N A/D converter power supply pin A/D converter external reference power supply pin A/D converter external reference power supply pin A/D converter power supply pin D/A converter external reference power supply pin D/A converter power supply pin DTMF output pin Circuit type Function
I General-purpose I/O port (STBC) Event output for channel 1 of the output compare I General-purpose I/O port (STBC) Event output for channel 2 of the output compare -- -- Power supply (3.0 V) input pin Power supply (3.0 V/5.0 V) input pin Power supply (0.0 V) input pin
*1: FPT-100P-M05 *2: FPT-100P-M06 Note: STBC = Incorporates standby control NMOS = N-ch open-drain output
12
To Top / Lineup / Index
MB90650A Series
s I/O CIRCUIT TYPE
Type A
X1
Circuit
Remarks * Oscillation feedback resistance : Approx. 1 M
X0
Standby control signal
B
X1A
* Oscillation feedback resistance : Approx. 10 M
X0A
Standby control signal
C
R Hysteresis input R
* Hysteresis input with pull-up Resistance approx. 50 k
D
Hysteresis input R
* Hysteresis input port
E
CTL
* Incorporates pull-up resistor control (for input) * CMOS level I/O Resistance approx. 50 k
CMOS R
F
CTL
* Incorporates pull-up resistor control (for input) * CMOS level output * Hysteresis input Resistance approx. 50 k
Hysteresis input R
(Continued)
13
To Top / Lineup / Index
MB90650A Series
Type G
Circuit
Open-drain control signal
Remarks * CMOS level I/O * Incorporates open-drain control
CMOS R
H
Open-drain control signal
* CMOS level output * Hysteresis input * Incorporates open-drain control
Hysteresis input R
I
* CMOS level I/O
CMOS R
J
* CMOS level output * Hysteresis input
Hysteresis input R
K
Digital output Hysteresis input R
* Hysteresis input * N-ch open-drain output
L
* CMOS level I/O * Analog input
CMOS R
Analog input
(Continued)
14
To Top / Lineup / Index
MB90650A Series
(Continued)
Type M Circuit Remarks * CMOS level I/O * Analog output * Shared with D/A outputs
D/A output CMOS R
N
R R
* DTMF analog output
R
15
To Top / Lineup / Index
MB90650A Series
s HANDLING DEVICES
1. Preventing Latch-up
Latch-up occurs in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if the voltage applied between VCC and VSS exceeds the rating. If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation. For the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage.
2. Treatment of Unused Pins
Leaving unused input pins unconnected can cause misoperation. Always pull-up or pull-down unused pins.
3. External Reset Input
To reliably reset the controller by inputting an "L" level to the RST pin, ensure that the "L" level is applied for at least five machine cycles. Take particular note when using an external clock input.
4. VCC and VSS Pins
Ensure that all VCC pins are at the same voltage. The same applies for the VSS pins.
5. Precautions when Using an External Clock
Drive the X0 pin only when using an external clock. * Using an external clock
MB90650A Series X0
X1
6. A/D Converter Power Supply and the Turn-on Sequence for Analog Inputs
Always turn off the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) before turning off the digital power supply (VCC). When turning the power on or off, ensure that AVRH does not exceed AVCC. Also, when using the analog input pins as input ports, ensure that the input voltage does not exceed AVCC.
7. Turn-on Sequence for D/A Converter Power Supply
Always turn on the D/A converter power supply (DVR), after turning off the digital power supply (VCC). And in the turning off the power supply sequence always turn off the digital power supply (VCC) after turning off the D/A converter power supply (DVR).
16
To Top / Lineup / Index
MB90650A Series
8. Initializing
In this device there are some kinds of inner resisters which are initializid only by power on reset. It is possible to initialize these resisters by turning on the power supply again.
9. Power Supply Pins
When there are several VCC and VSS pins, those pins that should have the same electric potential are connected within the device when the device is designed in order to prevent misoperation, such as latchup. However, all of those pins must be connected to the power supply and ground externally in order to reduce unnecessary emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the total output current standards. In addition, give a due consideration to the connection in that current supply be connected to VCC and VSS with the lowest possible impedance. Finally, it is recommended to connect a capacitor of about 0.1 F between VCC and VSS near this device as a bypass capacitor.
10.Crystal Oscillation Circuit
Noise in the vicinity of the X0 and X1 pins will cause this device to operate incorrectly. Design the printed circuit board so that the bypass capacitor connecting X0, X1 and the crystal oscillator (or ceramic oscillator) to ground is located as close to the device as possible, and that the wiring does not closs the other wirings. In addition, because printed circuit board artwork in which the area around the X0 and X1 pins is surrounded by ground provides stable operation, such an arrangement is strongly recommended.
11. About 2 Power Supplies
The MB90650A series usually uses the 3-V power supply as the main power source. With Vcc1 = 3 V and Vcc2 = 5 V, however, it can interface with P20 to P27, P30 to P37, P40 to P47, and P70 to P72 for the 5-V power supply separately from the 3-V power supply. Note, however, that the analog power supplies such as A/D and D/A can be used only as 3-V power supplies.
17
To Top / Lineup / Index
MB90650A Series
s PROGRAMMING FOR MB90P653A
In EPROM mode, the MB90P653A functions equivalent to the MBM27C1000/1000A. This allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter (do not use the electronic signature mode).
1. Program Mode
When shipped from Fujitsu, and after each erasure, all bits (128 K x 8 bits) in the MB90P653A are in the "1" state. Data is written to the ROM by selectively programming "0" into the desired bit locations. Bits cannot be set to "1" electrically.
2. Programming Procedure
(1) Set the EPROM programmer to MBM27C1000/1000A. (2) Load program data into the EPROM programmer at 00000H to 1FFFFH. Note that ROM addresses FE0000H to FFFFFFH in the operation mode in the MB90P653A series assign to 00000H to 1FFFFH in the EPROM mode (on the EPROM programmer).
Normal operating mode FFFFFF H 1FFFF H EPROM mode
PROM
PROM
FE0000 H 010000 H PROM 004000 H Mirror
00000 H
000000 H
The 00 bank PROM mirror is 48 Kbytes. (This is a mirror for FF4000H to FFFFFFH.) (3) Mount the MB90P653A on the adapter socket, then fit the adapter socket onto the EPROM programmer. When mounting the device and the adapter socket, pay attention to their mounting orientations. (4) Start programming the program data to the device. (5) If programming has not successfully resulted, connect a capacitor of approx. 0.1 F between VCC and GND, between VPP and GND. Note: The mask ROM products (MB90653A, MB90652A) does not support EPROM mode. Data cannot, therefore, be read by the EPROM programmer.
18
To Top / Lineup / Index
MB90650A Series
3. EPROM Programmer Socket Adapter
Part no. Package Compatible socket adapter Sun Hayato Co., Ltd.
MB90652APFV MB90653APFV MB90P653APFV MB90652APF MB90653APF MB90P653APF
LQFP-100 ROM-100SQF-32DP-16L
QFP-100 ROM-100QF-32DP-16L
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106
4. Recommended Screening Conditions
High temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
5. Programming Yeild
MB90P653A cannot be write tested for all bits due to their nature. Therefore the write yield cannot always be guaranteed to be 100%.
19
To Top / Lineup / Index
MB90650A Series
6. EPROM Mode Pin Assignments
* MBM27C1000/1000A compatible pins MBM27C1000/1000A Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name VPP OE A15 See "PIN ASSIGNMENT" A12 A07 A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 GND MB90P653A Pin no. Pin name MD2 P32 P17 P14 P27 P26 P25 P24 P23 P22 P21 P20 P00 P01 P02 VSS MBM27C1000/1000A Pin no. 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Pin name VCC PGM N.C. A13 A08 A09 A11 A16 A10 CE D07 D06 D05 D04 D03 See "PIN ASSIGNMENT" A14 MB90P653A Pin no. Pin name VCC P33 -- P16 P15 P10 P11 P13 P30 P12 P31 P07 P06 P05 P04 P03
* Non-MBM27C1000/1000A compatible pins Pin no. Pin name MD0 MD1 X0 X0A X1 to X1A See "PIN ASSIGNMENT" AVCC AVRH P37 P40 to P47 P50 to P57 P60 to P67 P70 to P74 P80 to P86 P90 to P97 PA0 to PA2 N.C. TEST Treatment Connect a pull-up resistor of 4.7 k. OPEN
* Power supply, GND connection pins Classification Power supply Pin no. See "PIN ASSIGNMENT" Pin name HST VCC DVRH P34 P35 P36 RST AVRL AVSS DVSS VV
GND
See "PIN ASSIGNMENT"
Connect a pull-up resistor of about 1 M to each pin.
20
To Top / Lineup / Index
MB90650A Series
s BLOCK DIAGRAM
X0, X1 RST X0A, X1A
5
Clock control circuit
CPU F2MC-16L family core Interrupt controller
RAM 2 8/16-bit PPG 2 (Output switching) x 1 channel
ROM
PPG00, PPG01 PPG10, PPG11
Communications prescaler
8/16-bit up/down counter/timer 8 bits x 2 channels (16 bits x 1 channel)
2 2 2
AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1
SIN0 SOT0 SCK0 2 2 2
UART
Internal data bus
Prescaler 6 2
CKOT
SIN1, SIN2 SOT1, SOT2 SCK1, SCK2 AVCC AVRH, AVRL AVSS ADTG AN0 to AN7 DA00, DA01 DVRH DVSS
I/O extended serial interface x 2 channels
DTP/external interrupt
IRQ0 to IRQ5 IRQ6, IRQ7
16-bit I/O timers 2 A/D converter (10 bits) 8 DTMF 2 D/A converter (8 bits) I2C interface 16-bit input capture x 2 channels 16-bit output compare x 4 channels 16-bit free-run timer x 1 channel
2 4
IN0, IN1 OUT1 to OUT3
DTMF SCL SDA
I/O ports 8 Other pins TEST, AD00 to AD15, A16 to A23, ALE, RD, WRL, WRH, HRQ, HAK, RDY, CLK, N.C., MD0 to MD2, VCC, VSS P00 to P07 8 P10 to P17 8 P20 to P27 8 P30 to P37 8 P40 to P47 8 P50 to P57 8 P60 to P67 5 P70 to P74 7 P80 to P86 8 P90 to P97 3 PA0 to PA2
P00 to P07 (8 pins) : Incorporates a pull-up resistor setting register (for input) P10 to P17 (8 pins) : Incorporates a pull-up resistor setting register (for input) P60 to P67 (8 pins) : Incorporates a pull-up resistor setting register (for input) P40 to P46 (7 pins) : Incorporates an open-drain setting register P47, P70 to P72 (4 pins) : Open-drain
21
To Top / Lineup / Index
MB90650A Series
s MEMORY MAP
* MB90652, MB90653, MB90P653
Single chip mode Internal ROM/external bus mode External ROM/external bus mode
FFFFFFH
ROM area Address #1
ROM area
FE0000H
010000H ROM area (FF bank image) Address #2 ROM area (FF bank image)
004000H 002000H Address #3
RAM 000100H 0000C0H
Registers
RAM
Registers
RAM
Registers
Peripherals 000000H
Peripherals
Peripherals
Type MB90652 MB90653 MB90P653
Address #1 * FF0000H FE0000H FE0000H
Address #2 * 004000H 004000H 004000H
Address #3 * 000CFFH 0014FFH 0014FFH
: Internal access memory : External access memory : No access * : Address #1, #2, and #3 are different owing to their devices respectively.
Notes: While the ROM data image of bank FF can be seen in the upper portion of bank 00, this is done only to permit effective use of the C compiler's small model. Because the lower 16 bits are the same, it is possible to reference tables in ROM without declaring the "far" specification in the pointer. For example, to access to 00C000H is to access to the ROM content of FFC000H in practice. Because the ROM area of FF bank exceeds 48 Kbytes, all the area can be seen in bank 00. So, the image for FF4000H to FFFFFFH can be seen in bank 00, while FE0000H to FF3FFFH can only be seen in bank FF and FE. 22
To Top / Lineup / Index
MB90650A Series
* MB90654A, MB90F654A
FFFFFFH
ROM area
010000H
ROM area (FF bank image)
ROM area (FF bank image)
002100H
RAM 000100H 0000C0H
Registers
RAM
Registers
RAM
Registers
Peripherals 000000H
Peripherals
Peripherals
Type MB90654A* MB90F654A*
Address #1 FC0000H FC0000H
Address #2 004000H 004000H
Address #3 0020FFH 0020FFH
: Internal access memory : External access memory : No access * : In the MB90654A and MB90F654A, RAM area 2000H is 2100H.
Notes: While the ROM data image of bank FF can be seen in the upper portion of bank 00, this is done only to permit effective use of the C compiler's small model. Because the lower 16 bits are the same, it is possible to reference tables in ROM without declaring the "far" specification in the pointer. For example, to access to 00C000H is to access to the ROM content of FFC000H in practice. Because the ROM area of FF bank exceeds 48 Kbytes, all the area can be seen in bank 00. So, the image for FF4000H to FFFFFFH can be seen in bank 00, while FE0000H to FF3FFFH can only be seen in bank FF and FE.
23
To Top / Lineup / Index
MB90650A Series
s F2MC-16L CPU PROGRAMMING MODEL
* Dedicated registers
AH AL USP SSP PS PC USPCU SSPCU USPCL SSPCL DPR PCB DTB USB SSB ADB 8 bits 16 bits 32 bits Accumulator User stack pointer System stack pointer Processor status Program counter User stack upper register System stack upper register User stack lower register System stack lower register Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register
* General-purpose registers
Maximum 32 banks
R7 R5 R3 R1 RW3
R6 R4 R2 R0
RW7 RL3 RW6 RW5 RL2 RW4 RL1
RW2 RW1 RL0 000180H + RP x 10H RW0 16 bits
* Processor status (PS)
ILM RP
--
I
S
T
N CCR
Z
V
C
24
To Top / Lineup / Index
MB90650A Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH to 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Port 4 pin register Port 0 resistance register Port 1 resistance register Port 6 resistance register Analog input enable register Serial mode register 0 Serial control register 0 Serial input register/ serial output register 0 Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Register name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ODR4 RDR0 RDR1 RDR6 ADER SMR0 SCR0 SIDR/ SODR0 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W UART0 Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 4 Port 0 Port 1 Port 6 Port 5, A/D Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 1XXXXXXXB XXXXXXXXB XXXXXXXXB ---XX111B -XXXXXXXB XXXXXXXXB -----XXXB 0 00 0 00 00 B 0 00 0 00 00 B 0 00 0 00 00 B 0 00 0 00 00 B - 00 0 00 00 B 0 00 0 00 00 B 0 00 0 00 00 B - -- 0 0- -- B - 00 0 00 00 B 0 00 0 00 00 B - -- - -0 00 B - 00 0 00 00 B 0 00 0 00 00 B 0 00 0 00 00 B 0 00 0 00 00 B 1 11 1 11 11 B 00000000B 00000100B XXXXXXXXB
(Reserved area)
(Continued)
25
To Top / Lineup / Index
MB90650A Series
Address 23H 24H 25H 26H 27H 28H 29H 2AH 2BH to 2FH 30H 31H 32H 33H 34H to 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H to 4FH 50H
Register Serial status register 0 Serial mode control status register 0 Serial mode control status register 0 Serial data register 0 Clock division control register Serial mode control status register 1 Serial mode control status register 1 Serial data register 1 Interrupt/DTP enable register Interrupt/DTP source register Request level setting register
Register name SSR0 SMCS0 SMCS0 SDR0 CDCR SMCS1 SMCS1 SDR1 ENIR EIRR ELVR
Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name UART0 I/O extended serial interface 0
Communications prescaler
Initial value 0 00 0 1- 00 B ----0000B 0 00 0 00 10 B XXXXXXXXB 0---1111B ----0000B 0 00 0 00 10 B XXXXXXXXB 00000000B
I/O extended serial interface 1
(Reserved area) 0 00 0 00 00B 00000000B 00000000B 00000000B A/D converter R R/W R/W R/W R/W R/W Clock output control register D/A converter 0 00 0 00 00B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB -------0B -------0B ----0000B
DTP/external interrupts
(Reserved area) Control status register 1 Control status register 2 Data register 1 Data register 2 D/A converter data register 0 D/A converter data register 1 D/A control register channel 0 D/A control register channel 1 Clock control register ADCS1 ADCS2 ADCR1 ADCR2 DAT0 DAT1 DACR0 DACR1 CLKR R/W
(Reserved area) Reload register lower channel 0 Reload register upper channel 0 Reload register lower channel 1 Reload register upper channel 1 PPG0 operation mode control register channel 0 PPG1 operation mode control register channel 1 PPG0, PPG1 output control register channel 0, channel 1 PRLL0 PRLH0 PRLL1 PRLH1 PPGC0 PPGC1 PPGOE R/W R/W R/W R/W R/W R/W R/W 8/16-bit PPG XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0X000XX1B 0X 0 0 0 0 0 1B 00000000B
(Reserved area) Lower compare register channel 0 OCCP0 R/W 16-bit I/O timer output compare (channel 0 to channel 3) XXXXXXXXB
(Continued)
26
To Top / Lineup / Index
MB90650A Series
Address 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH to 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H to 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH
Register Upper compare register channel 0 Lower compare register channel 1 Upper compare register channel 1 Lower compare register channel 2 Upper compare register channel 2 Lower compare register channel 3 Upper compare register channel 3
Compare control status register channel 0 Compare control status register channel 1 Compare control status register channel 2 Compare control status register channel 3
Register name OCCP0 OCCP1 OCCP2 OCCP3 OCS0 OCS1 OCS2 OCS3
Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W
Resource name
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 - - 0 0B - - - 0 0 0 0 0B 0 0 0 0 - - 0 0B - - - 0 0 0 0 0B XXXXXXXXB
16-bit I/O timer Output compare (channel 0 to channel 3)
(Reserved area)
Lower input capture register channel 0 Upper input capture register channel 0 Lower input capture register channel 1 Upper input capture register channel 1
IPCP0 IPCP1 ICS0, 1 TCDTL TCDTH TCCS UDCR0 UDCR1 RCR0 RCR1 CSR0 CCRL0 CCRH0 CSR1
16-bit I/O timer Input capture (channel 0, channel 1)
XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 00 00 0 00B 0 0 0 0 0 0 0 0B
Input capture control status register Lower timer data register Upper timer data register Timer control status register Up/down count register channel 0 Up/down count register channel 1 Reload compare register channel 0 Reload compare register channel 1 Counter status register channel 0
(Reserved area) 16-bit I/O timer Free-run timer 0 0 0 0 0 0 0 0B 0 00 00 0 00 B 0 0 0 0 0 0 0 0B 0 00 00 0 00B 8/16-bit up/down counter/timer 0 0 0 0 0 0 0 0B 0 00 00 0 00B 0 00 00 0 00B 0 0 0 0 1 0 0 0B 8/16-bit up/down counter/timer 0 00 00 0 00B 0 00 00 0 00B 8/16-bit up/down counter/timer
(Reserved area) R W R/W
(Reserved area) Counter control register channel 0 Counter status register channel 1 R/W R/W
(Reserved area) Counter control register channel 1 CCRL1 R/W 0 0 0 0 0 0 0 0B
(Continued)
27
To Top / Lineup / Index
MB90650A Series
Address 7BH 7CH to 7FH 80H 81H 82H 83H 84H 85H to 87H 88H 89H 8A to 9EH 9FH A0H A1H A2H to A4H A5H A6H A7H A8H A9H AAH ABH to AFH
Register Counter control register channel 1
Register name CCRH1
Read/ write R/W
Resource name 8/16-bit up/down counter/timer
Initial value X0001000B
(Reserved area) I C bus status register I C bus control register I C bus clock control register I C bus address register I C bus data register DTMF control register DTMF data register Delayed interrupt generation/ release register Low-power consumption mode control register Clock selection register
2 2 2 2 2
IBSR IBCR ICCR IADR IDAR DTMC DTMD
R R/W R/W R/W R/W -- -- -- -- Delayed interrupt generation module Low-power consumption mode Low-power consumption mode
External bus pin control circuit External bus pin control circuit External bus pin control circuit
0 0 0 0 0 0 0 0B 0 00 00 0 00B I C interface
2
-- 0XXXXXB - XXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 00 X0 00 0B
(Reserved area)
(Reserved area) (Accessing 90H to 9EH is prohibited) DIRR LPMCR CKSCR R/W R/W R/W - - - - - - - 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B
(Reserved area)
Auto-ready function selection register
ARSR HACR ECSR WDTC TBTC WTC
W W W R/W R/W R/W
0 0 1 1 - - 0 0B 0 0 0 0 0 0 0 0B 0000*00-B XXXXX111B 1- - 00 0 00B 1X- 00000B
External address output control register Bus control signal selection register Watchdog timer control register Timebase timer control register Watch timer control register
Watchdog timer Timebase timer Watch timer
(Reserved area)
(Continued)
28
To Top / Lineup / Index
MB90650A Series
(Continued)
Address B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H to FFH About Programming R/W : Readable and writable R : Read only W : Write only Explanation of initial values 0: The initial value of this bit is "0". 1: The initial value of this bit is "1". * : The initial value of this bit is "0" or "1". X: The initial value of this bit is undefined. -: This bit is not used. The initial value is undefined. Note: Areas below address 0000FFH not listed in the table are reserved areas. These addresses are accessed by internal access. No access signals are output on the external bus. Register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Register name ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller Resource name Initial value 0 0 0 0 0 1 1 1B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B 0 00 00 1 11B
(External area)
29
To Top / Lineup / Index
MB90650A Series
s INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER ASSIGNMENTS TO INTERRUPT SOURCES
Interrupt source Reset INT 9 instruction Exception A/D converter Timebase timer interval interrupt
DTP/external interrupt 0 (External interrupt 0) 16-bit free-run timer (I/O timer) overflow
I2OS support x x x x
Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF60H FFFF58H FFFF54H
Interrupt control register Number -- -- -- ICR00 ICR01 ICR02 ICR03 ICR04 Address -- -- -- 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H
I/O extended serial interface 1
DTP/external interrupt 1 (External interrupt 1)
I/O extended serial interface 2
DTP/external interrupt 2 (External interrupt 2) DTP/external interrupt 3 (External interrupt 3)
8/16-bit PPG 0 counter borrow
8/16-bit up/down counter/timer 0 compare
8/16-bit up/down counter/timer 0 underflow/overflow, up/down invert 8/16-bit PPG 1 counter borrow
DTP/external interrupt 4/5 (External interrupt 4/5) Output compare (channel 2) match (I/O timer) Output compare (channel 3) match (I/O timer)
ICR05
0000B5H
ICR06 ICR07 ICR08
0000B6H 0000B7H 0000B8H
Watch prescaler
DTP/external interrupt 6 (External interrupt 6) 8/16-bit up/down counter/timer 1 compare
x
#27 #28 #29 #30 #31 #32 #33 #34
8/16-bit up/down counter/timer 1 underflow/overflow, up/down invert
Input capture (channel 0) read (I/O timer) Input capture (channel 1) read (I/O timer) Output compare (channel 0) match (I/O timer) Output compare (channel 1) match (I/O timer) Completion of flash memory write/erase DTP/external interrupt 7 (External interrupt 7)
ICR09
0000B9H
ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH
x
#35 #36 #37 #39
UART0 receive complete UART0 transmit complete I C interface Delayed interrupt generation module
2
x x
#41 #42
: Indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal. : Indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (stop request present). : Indicates that the interrupt request flag is not cleared by the I2OS interrupt clear signal. Note: For resources in which two interrupt sources share the same interrupt number, the I2OS interrupt clear signal clears both interrupt request flags. 30
To Top / Lineup / Index
MB90650A Series
s PERIPHERAL RESOURCES
1. Parallel Ports
(1) I/O Ports Each port pin can be specified as either an input or output by its corresponding direction register when the pin is not set for use by a peripheral. When a port is set as an input, reading the data register always reads the value corresponding to the pin level. When a port is set as an output, reading the data register reads the data register latch value. The same applies when reading using a read-modify-write instruction. When used as control outputs, reading the data register reads the control output value, irrespective of the direction register value. Note that if a read-modify-write instruction (set bit or similar instruction) is used to set output data in the data register before switching a pin from input to output, the instruction reads the input level at the pin and not the data register latch value. * Block diagram
Data register read Internal data bus Data register Data register write Direction register Direction register write Pin
Direction register read
31
To Top / Lineup / Index
MB90650A Series
(2) Port Direction Registers
* Port 0 data register (PDR0) bit 7 Address : 000000H * Port 1 data register (PDR1) bit 15 Address : 000001H * Port 2 data register (PDR2) bit 7 Address : 000002H * Port 3 data register (PDR3) bit 15 Address : 000003H * Port 4 data register (PDR4) bit 7 Address : 000004H * Port 5 data register (PDR5) bit 15 Address : 000005H * Port 6 data register (PDR6) bit 7 Address : 000006H * Port 7 data register (PDR7) bit 15 Address : 000007H * Port 8 data register (PDR8) bit 7 Address : 000008H * Port 9 data register (PDR9) bit 15 Address : 000009H * Port A data register (PDRA) bit 7 Address : 00000AH -- bit 6 -- bit 5 -- bit 4 -- bit 3 -- bit 2 PA2 bit 1 PA1 bit 0 PA0 Initial value - - - - - XXXB Access R/W* P97 bit 14 P96 bit 13 P95 bit 12 P94 bit 11 P93 bit 10 P92 bit 9 P91 bit 8 P90 Initial value XXXXXXXXB Access R/W* -- bit 6 P86 bit 5 P85 bit 4 P84 bit 3 P83 bit 2 P82 bit 1 P81 bit 0 P80 Initial value - XXXXXXXB Access R/W* -- bit 14 -- bit 13 -- bit 12 P74 bit 11 P73 bit 10 P72 bit 9 P71 bit 8 P70 Initial value - - - XX111B Access R/W* P67 bit 6 P66 bit 5 P65 bit 4 P64 bit 3 P63 bit 2 P62 bit 1 P61 bit 0 P60 Initial value XXXXXXXXB Access R/W* P57 bit 14 P56 bit 13 P55 bit 12 P54 bit 11 P53 bit 10 P52 bit 9 P51 bit 8 P50 Initial value XXXXXXXXB Access R/W* P47 bit 6 P46 bit 5 P45 bit 4 P44 bit 3 P43 bit 2 P42 bit 1 P41 bit 0 P40 Initial value 1XXXXXXXB Access R/W* P37 bit 14 P36 bit 13 P35 bit 12 P34 bit 11 P33 bit 10 P32 bit 9 P31 bit 8 P30 Initial value XXXXXXXXB Access R/W* P27 bit 6 P26 bit 5 P25 bit 4 P24 bit 3 P23 bit 2 P22 bit 1 P21 bit 0 P20 Initial value XXXXXXXXB Access R/W* P17 bit 14 P16 bit 13 P15 bit 12 P14 bit 11 P13 bit 10 P12 bit 9 P11 bit 8 P10 Initial value XXXXXXXXB Access R/W* P07 bit 6 P06 bit 5 P05 bit 4 P04 bit 3 P03 bit 2 P02 bit 1 P01 bit 0 P00 Initial value XXXXXXXXB Access R/W*
R/W : Readable and writable -- : Unused X : Indeterminate
* : The operation of reading or writing to I/O ports is slightly different from reading or writing to memory, as follows. * Input mode Read: Reads the corresponding pin level. Write: Writes to the output latch. * Output mode Read: Reads the value of the data register latch. Write: The value is output from the corresponding pin.
32
To Top / Lineup / Index
MB90650A Series
(3) Port Direction Registers
* Port 0 direction register (DDR0) bit 7 Address : 000010H * Port 1 direction register (DDR1) bit 15 Address : 000011H * Port 2 direction register (DDR2) bit 7 Address : 000012H * Port 3 direction register (DDR3) bit 15 Address : 000013H * Port 4 direction register (DDR4) bit 7 Address : 000014H * Port 5 direction register (DDR5) bit 15 Address : 000015H * Port 6 direction register (DDR6) bit 7 Address : 000016H * Port 7 direction register (DDR7) bit 15 Address : 000017H * Port 8 direction register (DDR8) bit 7 Address : 000018H * Port 9 direction register (DDR9) bit 15 Address : 000019H * Port A direction register (DDRA) bit 7 Address : 00001AH -- bit 6 -- bit 5 -- bit 4 -- bit 3 -- bit 2 DA2 bit 1 DA1 bit 0 DA0 Initial value -----000B Access R/W* D97 bit 14 D96 bit 13 D95 bit 12 D94 bit 11 D93 bit 10 D92 bit 9 D91 bit 8 D90 Initial value 00000000B Access R/W* -- bit 6 D86 bit 5 D85 bit 4 D84 bit 3 D83 bit 2 D82 bit 1 D81 bit 0 D80 Initial value -0000000B Access R/W* -- bit 14 -- bit 13 -- bit 12 D74 bit 11 D73 bit 10 -- bit 9 -- bit 8 -- Initial value ---00---B Access R/W* D67 bit 6 D66 bit 5 D65 bit 4 D64 bit 3 D63 bit 2 D62 bit 1 D61 bit 0 D60 Initial value 00000000B Access R/W* D57 bit 14 D56 bit 13 D55 bit 12 D54 bit 11 D53 bit 10 D52 bit 9 D51 bit 8 D50 Initial value 00000000B Access R/W* -- bit 6 D46 bit 5 D45 bit 4 D44 bit 3 D43 bit 2 D42 bit 1 D41 bit 0 D40 Initial value -0000000B Access R/W* D37 bit 14 D36 bit 13 D35 bit 12 D34 bit 11 D33 bit 10 D32 bit 9 D31 bit 8 D30 Initial value 00000000B Access R/W* D27 bit 6 D26 bit 5 D25 bit 4 D24 bit 3 D23 bit 2 D22 bit 1 D21 bit 0 D20 Initial value 00000000B Access R/W* D17 bit 14 D16 bit 13 D15 bit 12 D14 bit 11 D13 bit 10 D12 bit 9 D11 bit 8 D10 Initial value 00000000B Access R/W* D07 bit 6 D06 bit 5 D05 bit 4 D04 bit 3 D03 bit 2 D02 bit 1 D01 bit 0 D00 Initial value 00000000B Access R/W*
R/W : Readable and writable -- : Unused
33
To Top / Lineup / Index
MB90650A Series
(Continued) * : The operation of reading or writing to I/O ports is slightly different from reading or writing to memory, as follows. * Input mode Read: Reads the corresponding pin level. Write: Writes to the output latch. * Output mode Read: Reads the value of the data register latch. Write: The value is output from the corresponding pin. When pins are used as ports, the register bits control the corresponding pins as follows. 0: Input mode 1: Output mode Bits are set to "0" by a reset.
* P47, P70 to P72 No DDR for this port. Data is always available in this port, so when using P70 and P71 as I2C pin, set PDR value to "1". (Otherwise when using P70 and P71 by themselves, turn off the I2C.) As this port is open-drain output style, so when using this port as an input port, in order to turn off the output transister, set the output data resister value to "1" and add the pull up resister to the external pin.
34
To Top / Lineup / Index
MB90650A Series
(4) Port Resistance Registers * Register configuration
* Port 0 resistance register (RDR0) bit 7 Address : 00001CH * Port 1 resistance register (RDR1) bit 15 Address : 00001DH * Port 6 resistance register (RDR6) bit 7 Address : 00001EH RD67 bit 6 RD66 bit 5 RD65 bit 4 RD64 bit 3 RD63 bit 2 RD62 bit 1 RD61 bit 0 RD60 Initial value Access 00000000B R/W RD17 bit 14 RD16 bit 13 RD15 bit 12 RD14 bit 11 RD13 bit 10 RD12 bit 9 RD11 bit 8 RD10 Initial value Access 00000000B R/W RD07 bit 6 RD06 bit 5 RD05 bit 4 RD04 bit 3 RD03 bit 2 RD02 bit 1 RD01 bit 0 RD00 Initial value Access 00000000B R/W
R/W : Readable and writable
* Block diagram
Pull-up resistor (approx. 50 k)
Internal data bus
Data register
Port I/O
Direction register
Resistance register
Notes: * Input resistance register R/W Controls the pull-up resistor in input mode. 0: Pull-up resistor disconnected in input mode. 1: Pull-up resistor connected in input mode. The setting has no meaning in output mode (pull-up resistor disconnected). The direction register (DDR) sets input or output mode. * The pull-up resistor is disconnected in hardware standby or stop mode (SPL = 1) (high impedance). * This function is disabled when using an external bus mode. In this case, do not write to this register.
35
To Top / Lineup / Index
MB90650A Series
(5) Port Pin Register * Register configuration
* Port 4 pin register (ODR4) bit 7 Address : 00001BH -- bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value Access -0000000B R/W
OD46 OD45 OD44 OD43 OD42 OD41 OD40
R/W : Readable and writable -- : Unused
* Block diagram
Internal data bus
Data register
Port I/O
Direction register
Pin register
Notes: * Pin register R/W Performs open-drain control in output mode. 0: Operate as a standard output port in output mode. 1: Operate as an open-drain output port in output mode. The setting has no meaning in input mode (output Hi-z). The direction register (DDR) sets input or output mode. * This function is disabled when using an external bus mode. In this case, do not write to this register. (6) Analog Input Enable Register * Register configuration
* Analog input enable register (ADER) bit 15 Address : 00001FH bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Initial value Access 1 1 1 1 1 1 1 1 B R/W
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable and writable
Controls each port 5 pin as follows. 0: Port input mode 1: Analog input mode Set to "1" by a reset. 36
To Top / Lineup / Index
MB90650A Series
2. UART
The UART is a serial I/O port that can be used for CLK asynchronous (start-stop synchronization) or CLK synchronous communications. The UART has the following features. * * * * Full duplex, double buffered Supports asynchronous (start-stop synchronization) and CLK synchronous data transfer Supports multi-processor mode Built-in dedicated baud rate generator
Asynchronous : 9615 bps, 31250 bps, 4808 bps, 2404 bps and 1202 bps For a 6, 8, 10, 12, or 16 MHz CLK synchronous : 1 Mbps, 500 kbps, 250 kbps, 125 kbps, 115.2 kbps and 62.5 kbps clock.
* * * *
Supports flexible baud rate setting using an external clock Error detect function (parity, framing, and overrun) NRZ type transmission signal Intelligent I/O service support
(1) Register Configuration
bit 15 CDCR SCR SSR 8 bits * Serial mode register 0 (SMR0) bit 7 Address : 000020H * Serial control register 0 (SCR0) MD1 R/W bit 15 Address : 000021H PEN bit 6 MD0 R/W bit 14 P bit 5 CS2 R/W bit 13 SBL R/W bit 5 D5 R/W bit 13 FRE R bit 13 -- -- bit 4 CS1 R/W bit 12 CL R/W bit 4 D4 R/W bit 12 bit 3 bit 2 bit 1 bit 0 SOE R/W bit 8 TXE R/W bit 0 D0 R/W bit 8 TIE R/W bit 8 DIV0 R/W Initial value 0---1111B Initial value 00001-00B Initial value XXXXXXXXB Initial value 00000100B Initial value 00000000B bit 8 bit 7 -- SMR SIDR (R) /SODR (W) 8 bits bit 0
CS0 Reserved SCKE R/W bit 11 A/D R/W bit 3 D3 R/W bit 11 R/W bit 10 REC W bit 2 D2 R/W bit 10 -- -- bit 10 DIV2 R/W R/W bit 9 RXE R/W bit 1 D1 R/W bit 9 RIE R R/W bit 9 DIV1 R/W
R/W R/W * Serial input register/serial output register 0 (SIDR/SODR0) bit 7 Address : 000022H * Serial status register 0 (SSR0) D7 R/W bit 15 Address : 000023H * Clock division control register (CDCR) PE R bit 15 Address : 000027H MD R/W R/W : R: W: --: X: Readable and writable Read only Write only Unused Indeterminate bit 6 D6 R/W bit 14 ORE R bit 14 -- --
RDRF TDRE R bit 12 -- -- R bit 11 DIV3 R/W
37
To Top / Lineup / Index
MB90650A Series
(2) Block Diagram
Control signals
Reception interrupt (to CPU)
Dedicated baud rate generator 16-bit timer 0 (Connected internally) Transmission clock pulses Clock select circuit Reception clock pulses
SCK0, SCK1 Transmission interrupt (to CPU)
External clock Reception control circuit SIN0 Start bit detection circuit Reception bit counter Reception parity counter Transmission control circuit Transmission start circuit Transmission bit counter Transmission parity counter
SOT0, SOT1
Reception status determination circuit
Reception shifter
Transmission shifter
Reception error occurrence signal for I2OS (to CPU)
End of reception SIDR
Start of transmission SODR
Internal data bus
SMR register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR register
PEN P SBL CL A/D REC RXE TXE
SSR register
PE ORE FRE RDRF TDRE RIE TIE
Control signals
38
To Top / Lineup / Index
MB90650A Series
3. I/O Extended Serial Interface
I/O extended serial interface consists of an 8-bit serial I/O interface that can perform clock synchronous data transfer. Either LSB-first or MSB-first data transfer can be selected. The following two serial I/O operation modes are available. * Internal shift clock mode: Data transfer is synchronized with the internal clock. * External shift clock mode: Data transfer is synchronized with the clock input from the external pin (SCK). By manipulating the general-purpose port that shares the external pin (SCK), this mode also enables the data transfer operation to be driven by CPU instructions. (1) Register Details
* Serial mode control status register 0, 1 (SMCS0, SMCS1) bit 15 Address : 000025H 000029H bit 14 bit 13 bit 12 SIE R/W bit 4 -- -- bit 11 SIR R/W
*1
bit 10
bit 9
bit 8
Initial value 00000010B
SMD2 SMD1 SMD0 R/W bit 7 R/W bit 6 -- -- R/W bit 5 -- --
BUSY STOP STRT R bit 2 BDS R/W R/W bit 1 SOE R/W R/W
*2
bit 3 MODE R/W
bit 0 SCOE R/W
Initial value ----0000B
Address : 000024H 000028H
-- --
* Serial data register 0, 1 (SDR0, SDR1) bit 7 Address : 000026H 00002AH R/W : R: --: X: D7 R/W Readable and writable Read only Unused Indeterminate bit 6 D6 R/W bit 5 D5 R/W bit 4 D4 R/W bit 3 D3 R/W bit 2 D2 R/W bit 1 D1 R/W bit 0 D0 R/W Initial value XXXXXXXXB
*1: Only "0" can be written. *2: Only "1" can be written. Reading always returns "0". This register controls the transfer operation mode of the serial I/O. The following describes the function of each bit. bit 3: Serial mode selection bit (MODE) This bit selects the conditions for starting operation from the halted state. Changing the mode during operation is prohibited MODE 0 1 Operation Start when STRT is set to "1". [Initial value] Start on reading from or writing to the serial data register.
The bit is initialized to "0" by a reset. The bit is readable and writable. Set to "1" when using the intelligent I/O service. bit 2: Transfer direction selection bit (BDS: Bit Direction Select) Selects as follows at the time of serial data input and output whether the data are to be transferred in the order from LSB to MSB or vice versa. MODE 0 1 LSB-first [Initial value] MSB-first 39 Operation
To Top / Lineup / Index
MB90650A Series
(2) Block Diagram
Internal data bus (MSB-first) D0 to D7 SIN1, SIN2 SDR (Serial data register) SOT1, SOT2 Read Write D7 to D0 (LSB-first) Transfer direction selection
SCK1, SCK2 Control circuit Shift clock counter
Internal clock
2
1
0
SIE SIR BUSY STOP STRT MODE BDS SOE SCOE
SMD2 SMD1 SMD0
Interrupt request Internal data bus
40
To Top / Lineup / Index
MB90650A Series
4. A/D Converter
The A/D converter converts analog input voltages to digital values. The A/D converter has the following features. Conversion time: Minimum of 5.2 s per channel (for a 16 MHz machine clock) Uses RC-type successive approximation conversion with a sample and hold circuit. 10-bit resolution Eight program-selectable analog input channels Single conversion mode: Selectively convert a one channel. Scan conversion mode: Continuously convert multiple channels. Maximum of 8 programselectable channels. Continuous conversion mode : Repeatedly convert specified channels. Stop conversion mode: Convert one channel then halt until the next activation. (Enables synchronization of the conversion start timing.) * An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D conversion. This interrupt can activate I2OS to transfer the result of A/D conversion to memory and is suitable for continuous operation. * Activation by software, external trigger (falling edge), or timer (rising edge) can be selected. * * * * (1) Register Configuration
bit 15 ADCS2 ADCR2 8 bits * Control status register 1 (ADCS1) bit 7 Address : 000036H * Control status register 2 (ADCS2) MD1 R/W bit 15 Address : 000037H * Data register 1 (ADCR1) BUSY R/W bit 7 Address : 000038H * Data register 2 (ADCR2) 7 R bit 15 Address : 000039H -- R R/W : Readable and writable R : Read only X : Indeterminate bit 6 MD0 R/W bit 14 INT R/W bit 6 6 R bit 14 -- R bit 5
bit 8 bit 7 ADCS1 ADCR1 8 bits
bit 0
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value 00000000B
ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 R/W bit 13 INTE R/W bit 5 5 R bit 13 -- R R/W bit 12 R/W bit 11 R/W bit 10 STS0 R/W bit 2 2 R bit 10 -- R R/W bit 9 STRT R/W bit 1 1 R bit 9 9 R R/W bit 8 DA R/W bit 0 0 R bit 8 8 R
Initial value 00000000B
PAUS STS1 R/W bit 4 4 R bit 12 -- R R/W bit 3 3 R bit 11 -- R
Initial value XXXXXXXXB
Initial value XXXXXXXXB
41
To Top / Lineup / Index
MB90650A Series
(2) Block Diagram
AVCC
AVRH AVRL
AVSS
D/A converter MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input circuit
Successive approximation register
Comparator Internal data bus Decoder Data register ADCR1, ADCR2 A/D control register 1 A/D control register 2 Trigger activation PPG01 Timer activation Operating clock ADCS1, ADCS2 Prescaler
Sample and hold circuit
ADTG
42
To Top / Lineup / Index
MB90650A Series
5. D/A Converter
D/A converter is an R-2R type D/A converter with 8-bit resolution. The device contains two D/A converters. The D/A control register controls the output of the two D/A converters independently. (1) Register Configuration
* D/A converter data register 0 (DAT0) bit 7 Address : 00003AH * D/A converter data register 1 (DAT1) DA07 R/W bit 15 Address : 00003BH * D/A control register channel 0 (DACR0) DA17 R/W bit 7 Address : 00003CH * D/A control register channel 1 (DACR1) -- -- bit 15 Address : 00003DH -- -- R/W : Readable and writable -- : Unused X : Indeterminate bit 6 DA06 R/W bit 14 DA16 R/W bit 6 -- -- bit 14 -- -- bit 5 DA05 R/W bit 13 DA15 R/W bit 5 -- -- bit 13 -- -- bit 4 DA04 R/W bit 12 DA14 R/W bit 4 -- -- bit 12 -- -- bit 3 DA03 R/W bit 11 DA13 R/W bit 3 -- -- bit 11 -- -- bit 2 DA02 R/W bit 10 DA12 R/W bit 2 -- -- bit 10 -- -- bit 1 DA01 R/W bit 9 DA11 R/W bit 1 -- -- bit 9 -- -- bit 0 DA00 R/W bit 8 DA10 R/W bit 0 DAE0 R/W bit 8 DAE1 R/W Initial value -------0B Initial value -------0B Initial value XXXXXXXXB Initial value XXXXXXXXB
43
To Top / Lineup / Index
MB90650A Series
(2) Block Diagram
Internal data bus
DA DA DA DA DA DA DA DA 17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA 07 06 05 04 03 02 01 00
DVR DA17 2R DA16 2R DA15 R DA07
DVR
2R DA06 2R DA05
R
R
R
DA11 2R DA10 R
DA01 2R DA00 R
2R 2R DAE1 Standby control
2R 2R DAE0 Standby control
DA output channel 1
DA output channel 0
44
To Top / Lineup / Index
MB90650A Series
6. 8/16-bit PPG
8/16-bit PPG is an 8-bit reload timer module. The block performs PPG output in which the pulse output is controlled by the operation of the timer. The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. The PPG has the following functions. * 8-bit PPG output in two channels independent operation mode: Two independent PPG output channels are available. * 16-bit PPG output operation mode : One 16-bit PPG output channel is available. * 8 + 8-bit PPG output operation mode : Variable-period 8-bit PPG output operation is available by using the output of channel 0 as the clock input to channel 1. * PPG output operation : Outputs pulse waveforms with variable period and duty ratio. Can be used as a D/A converter in conjunction with an external circuit. (1) Register Configuration
* PPG0 operation mode control register channel 0 (PPGC0) bit 7 Address : 000044H PEN0 R/W * PPG1 operation mode control register channel 1 (PPGC1) bit 15 Address : 000045H PEN1 R/W bit 14 -- -- bit 13 PE10 R/W bit 12 PIE1 R/W bit 11 PUF1 R/W bit 10 MD1 R/W bit 9 bit 8 Initial value 0X000001B bit 6 -- -- bit 5 PE00 R/W bit 4 PIE0 R/W bit 3 PUF0 R/W bit 2 -- -- bit 1 -- -- bit 0 Reserved -- Initial value 0X000XX1B
MD0 Reserved R/W --
* PPG0, PPG1 output control register channel 0, channel 1 (PPGOE) bit 7 Address : 000046H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PE01 R/W Initial value 00000000B
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 R/W R/W R/W R/W R/W R/W R/W
* Reload register upper channel 0, channel 1 (PRLH0, PRLH1) bit 15 Address : 000041H 000043H R/W R/W R/W R/W R/W R/W R/W R/W bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Initial value XXXXXXXXB
* Reload register lower channel 0, channel 1 (PRLL0, PRLL1) bit 7 Address : 000040H 000042H R/W R/W R/W R/W R/W R/W R/W R/W bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXXB
R/W : Readable and writable X : Indeterminate
45
To Top / Lineup / Index
MB90650A Series
(2) Block Diagram * 8/16-bit PPG (channel 0)
PPG00 output enable
Peripheral clock divided by 16 Peripheral clock divided by 8 Peripheral clock divided by 4 Peripheral clock divided by 2 Peripheral clock
PPG00 PPG01
PPG01 output enable A/D converter PPG0 output latch Invert Clear PEN0
PCNT (Down-counter) Count clock selection Timebase counter output Main clock divided by 512 L/H select Reload
S RQ
IRQ
Channel 1-borrow L/H selector
PRLL0
PRLBH0 PIE0
PRLH0
PUF0 L-side data bus H-side data bus
PPGC0 (Operation mode control)
46
To Top / Lineup / Index
MB90650A Series
* 8/16-bit PPG (channel 1)
PPG10 output enable
Peripheral clock divided by 16 Peripheral clock divided by 8 Peripheral clock divided by 4 Peripheral clock divided by 2 Peripheral clock
PPG10 PPG11
PPG11 output enable UART PPG1 output latch Invert Clear
Count clock selection PEN1
PCNT (Down-counter) Channel 0-borrow Timebase counter output Main clock divided by 512 L/H select Reload L/H selector
S RQ
IRQ
PRLL1
PRLBH1 PIE
PRLH1
PUF L-side data bus H-side data bus
PPGC1 (Operation mode control)
47
To Top / Lineup / Index
MB90650A Series
7. 8/16-bit Up/Down Counter/Timer
8/16-bit up/down counter/timer is an up/down counter/timer and consists of six event input pins, two 8-bit up/ down counters, two 8-bit reload/compare registers, and their control circuits. (1) Main Functions * The 8-bit count register can count in the range 0 to 256 (or 0 to 65535 in 1 x 16-bit operation mode). * The count clock selection can select between four different count modes. Count modes Timer mode Up/down counter mode Phase difference count mode (x 2) Phase difference count mode (x 8) * Two different internal count clocks are available in timer mode. Count clock (at 16 MHz operation) 125 ns (8 MHz: Divide by 2) 0.5 s (1 MHz: Divide by 8) * In up/down count mode, you can select which edge to detect on the external pin input signal. Detected edge Detect falling edges Detect rising edges Detect both rising and falling edges Edge detection disabled * Phase difference count mode is suitable for motor encoder counting. By inputting the A, B, and Z phase outputs from the encoder, a high-precision rotational angle, speed, or similar count can be implemented simply. * Two different functions can be selected for the ZIN pin. ZIN pin Counter clear function Gate function * Compare and reload functions are available and can be used either independently or together. A variablewidth up/down count can be performed by activating both functions. Compare/reload function Compare function (Output an interrupt when a compare occurs.) Compare function (Output an interrupt and clear the counter when a compare occurs.) Reload function (Output an interrupt and reload when an underflow occurs.) Compare/reload function (Output an interrupt and clear the counter when a compare occurs. Output an interrupt and reload when an underflow occurs.) Compare/reload disabled * Whether or not to generate an interrupt when a compare, reload (underflow), or overflow occurs can be set independently. * The previous count direction can be determined from the count direction flag. * An interrupt can be generated when the count direction changes.
48
To Top / Lineup / Index
MB90650A Series
(2) Register Configuration
bit 15 UDCR1 RCR1 (Reversed area) CCRH0 (Reversed area) CCRH1 8 bits * Up/down count register channel 0 (UDCR0) bit 7 Address : 000070H * Up/down count register channel 1 (UDCR1) D07 R bit 15 Address : 000071H * Reload compare register channel 0 (RCR0) D17 R bit 7 Address : 000072H * Reload compare register channel 1 (RCR1) D07 W bit 15 Address : 000073H D17
bit 8 bit 7 UDCR0 RCR0 CSR0 CCRL0 CSR1 CCRL1 8 bits
bit 0
bit 6 D06 R bit 14 D16 R bit 6 D06 W bit 14 D16
bit 5 D05 R bit 13 D15 R bit 5 D05 W bit 13 D15 W bit 5 UDIE R/W bit 5
bit 4 D04 R bit 12 D14 R bit 4 D04 W bit 12 D14 W bit 4
bit 3 D03 R bit 11 D13 R bit 3 D03 W bit 11 D13 W bit 3
bit 2 D02 R bit 10 D12 R bit 2 D02 W bit 10 D12 W bit 2
bit 1 D01 R bit 9 D11 R bit 1 D01 W bit 9 D11 W bit 1
bit 0 D00 R bit 8 D10 R bit 0 D00 W bit 8 D10 W bit 0 UDF0 R bit 0
Initial value 00000000B
Initial value 00000000B
Initial value 00000000B
Initial value 00000000B
W W * Counter status register channel 0, channel 1 (CSR0, CSR1) bit 7 Address : 000074H 000078H CSTR bit 6 CITE
Initial value 00000000B
CMPF OVFF UDFF UDF1 R/W bit 4 R/W bit 3 R/W bit 2 R bit 1
R/W R/W * Counter control register channel 0, channel 1 (CCRL0, CCRL1) bit 7 Address : 000076H 00007AH * Counter control register channel 0 (CCRH0) - - bit 15 Address : 000077H * Counter control register channel 1 (CCRH1) bit 6
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 R/W bit 14 R/W bit 13 CFIE R/W bit 13 CFIE R/W R/W bit 12 R/W bit 11 R/W bit 10 R/W bit 9 R/W bit 8 CES0 R/W bit 8 CES0 R/W
Initial value 00001000B 00000000B
Initial value 00000000B
M16E CDCF R/W bit 15 R/W bit 14 CDCF R/W
CLKS CMS1 CMS0 CES1 R/W bit 12 R/W bit 11 R/W bit 10 R/W bit 9
Initial value X0001000B
Address : 00007BH
- -
CLKS CMS1 CMS0 CES1 R/W R/W R/W R/W
R/W : R: W: -: X:
Readable and writable Read only Write only Unused Indeterminate
49
To Top / Lineup / Index
MB90650A Series
(3) Block Diagram * 8/16-bit up/down counter/timer (channel 0)
Internal data bus
8 bits CGE1 CGE0 C/GS
RCR0 (Reload/compare register 0)
CTUT
ZIN0
Edge or level detection
Reload control
UCRE
RLDE
UDCC
Counter clear 8 bits UDCR0 (Up/down count register 0) Carry CMPF
CES1 CES0 CMS1 CMS0 CITE AIN0 BIN0 Count clock UDF1 UDF0 CDCF CFIE Interrupt output
UDFF OVFF UDIE
Up/down count clock selection
Prescaler
CSTR
CLKS
50
To Top / Lineup / Index
MB90650A Series
* 8/16-bit up/down counter/timer (channel 1)
Internal data bus
8 bits CGE1 CGE0 C/GS
RCR1 (Reload/compare register 1)
CTUT
ZIN1
Edge or level detection
Reload control
UCRE
RLDE
UDCC
Counter clear 8 bits UDCR1 (Up/down count register 1) CMPF UDFF OVFF
CMS1 CMS0 CES1 CES0 EN16 Carry CITE UDIE
Count clock
AIN1 BIN1 Up/down count clock selection UDF1 UDF0 CDCF CFIE
Prescaler
CSTR
Interrupt output
CLKS
51
To Top / Lineup / Index
MB90650A Series
8. Clock Output Control Register
Clock output control register outputs the divided machine clock. (1) Register Configuration
* Clock control register (CLKR) bit 7 Address : 00003EH -- bit 6 -- bit 5 -- bit 4 -- bit 3 bit 2 bit 1 bit 0 Initial value ----0000B
CKEN FRQ2 FRQ1 FRQ0 R/W R/W R/W R/W
R/W : Readable and writable -- : Unused
bit 3: Clock output enable bit (CKEN) MODE 0 1 Operate as a standard port. Operate as the clock output. Operation
bit 2 to bit 0: Clock output frequency select bit (FRQ2 to FRQ0) FRQ2 0 0 0 0 1 1 1 1 FRQ1 0 0 1 1 0 0 1 1 FRQ0 0 1 0 1 0 1 0 1 Output clock /2 /2
1 2
= 16 MHz 125 ns 250 ns 500 ns 1 s 2 s 4 s 8 s 16 s
= 8 MHz 250 ns 500 ns 1 s 2 s 4 s 8 s 16 s 32 s
= 4 MHz 500 ns 1 s 2 s 4 s 8 s 16 s 32 s 64 s
/23 /24 /2
5
/26 /27 /2
8
52
To Top / Lineup / Index
MB90650A Series
9. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the requests to the F2MC-16L CPU to activate the intelligent I/O service or interrupt processing. Two request levels ("H" and "L") are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts on a rising or falling edge as well as on "H" and "L" levels can be selected, giving a total of four types. (1) Register Configuration
* Interrupt/DTP enable register (ENIR) bit 7 Address : 000030H * Interrupt/DTP source register (EIRR) EN7 R/W bit 15 Address : 000031H * Request level setting register (ELVR) ER7 R/W bit 7 Address : 000032H LB3 R/W bit 15 Address : 000033H LB7 R/W R/W : Readable and writable bit 6 EN6 R/W bit 14 ER6 R/W bit 6 LA3 R/W bit 14 LA7 R/W bit 5 EN5 R/W bit 13 ER5 R/W bit 5 LB2 R/W bit 13 LB6 R/W bit 4 EN4 R/W bit 12 ER4 R/W bit 4 LA2 R/W bit 12 LA6 R/W bit 3 EN3 R/W bit 11 ER3 R/W bit 3 LB1 R/W bit 11 LB5 R/W bit 2 EN2 R/W bit 10 ER2 R/W bit 2 LA1 R/W bit 10 LA5 R/W bit 1 EN1 R/W bit 9 ER1 R/W bit 1 LB0 R/W bit 9 LB4 R/W bit 0 EN0 R/W bit 8 ER0 R/W bit 0 LA0 R/W bit 8 LA4 R/W Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B
(2) Block Diagram
4 Interrupt/DTP enable register Internal data bus 4 Gate 4 Interrupt/DTP source register 8 Request level setting register Request F/F Edge detect circuit 4
Request input
53
To Top / Lineup / Index
MB90650A Series
10. 16-bit I/O Timer
The 16-bit I/O timer consists of one 16-bit free-run timer, two output compare, and two input capture modules. Based on the 16-bit free-run timer, these functions can be used to generate two independent waveform outputs and to measure input pulse widths and external clock periods. * Register configuration
* 16-bit free-run timer bit 15 TCDTL : 000066H TCDTH : 000067H TCCS : 000068H * 16-bit output compare OCCP0 OCCP1 OCCP2 OCCP3 OCS0 OCS1 OCS2 OCS3 : : : : : : : : 000050H, 51H 000052H, 53H 000054H, 55H 000056H, 57H bit 15 OCCP bit 0 Compare register channel 0 to channel 3 lower, upper (OCCP0 to OCCP3) TCDT TCCS bit 0 Timer data register lower, upper (TCDTL, TCDTH) Timer control status register (TCCS)
000058H 000059H 00005AH 00005BH
OCS
Compare control status register channel 0 to channel 3 (OCS0 to OCS3)
* 16-bit input capture bit 15 IPCP0 : 000060H, 61H IPCP1 : 000062H, 63H ICS0, 1 : 000064H IPCP ICS bit 0 Input capture register channel 0, channel 1 lower, upper (IPCP0, IPCP1) Input capture control status register (ICS0, 1)
* Block diagram
Control logic Interrupt 16-bit free-run timer 16-bit timer Clear Internal data bus Output compare 0 Compare register 0 Output compare 1 Compare register 1 Output compare 2 Compare register 2 Output compare 3 Compare register 3 Input capture 0 Capture register 0
Edge selection
To each block
TQ
OUT0
TQ
OUT1
TQ
OUT2
TQ
OUT3
IN0
Capture register 1
Edge selection
IN1
54
To Top / Lineup / Index
MB90650A Series
(1) 16-bit Free-run Timer The 16-bit free-run timer consists of a 16-bit up-counter, a control register, and a prescaler. The output of the timer/counter is used as the base time for the input capture and output compare. * The operating clock for the counter can be selected from four different clocks. Four internal clocks (/4, /16, /32, /64) * Interrupts can be generated when a counter value overflow or compare match with compare register 0 occurs (the appropriate mode must be set for a compare match). * The counter can be initialized to 0000H by a reset, software clear, or compare match with compare register 0. * Register details
* Upper timer data register (TCDTH) bit 15 Address : 000067H T15 R/W * Lower timer data register (TCDTL) bit 7 Address : 000066H T07 R/W bit 6 T06 R/W bit 5 T05 R/W bit 4 T04 R/W bit 3 T03 R/W bit 2 T02 R/W bit 1 T01 R/W bit 0 T00 R/W Initial value 00000000B bit 14 T14 R/W bit 13 T13 R/W bit 12 T12 R/W bit 11 T11 R/W bit 10 T10 R/W bit 9 T09 R/W bit 8 T08 R/W Initial value 00000000B
R/W : Readable and writable
The count value of the 16-bit free-run timer can be read from this register. The count is cleared to "0000B" by a reset. Writing to this register sets the timer value. However, only write to the register when the timer is halted (STOP = "1"). Always use word access. The 16-bit free-run timer is initialized by the following. * Reset * The clear bit (CLR) of the control status register * A match between the timer/counter value and compare register 0 of the output compare (if the appropriate mode is set) * Block diagram
Interrupt request
IVF
IVFE STOP MODE CLR
CLK1 CLK0
Divider
Internal data bus
Comparator 0
16-bit up-counter
Clock
Count value output T15 to T00
55
To Top / Lineup / Index
MB90650A Series
(2) Output Compare The output compare consists of two 16-bit compare registers, compare output latches, and control registers. The modules can invert the output level and generate an interrupt when the 16-bit free-run timer value matches the compare register value. * The four compare registers can be operated independently. Each compare register has a corresponding output pin and interrupt flag. * The four compare registers can be paired to control the output pins. Invert the output pins using the four compare registers. * Initial values can be set for the output pins. * An interrupt can be generated when a compare match occurs. * Register configuration
* Upper compare register channel 0 to channel 3 (OCCP0 to OCCP3) OCCP0 OCCP1 OCCP2 OCCP3 : : : : 000051H 000053H 000055H 000057H bit 15 C15 R/W bit 14 C14 R/W bit 13 C13 R/W bit 12 C12 R/W bit 4 C04 R/W bit 12 bit 11 C11 R/W bit 3 C03 R/W bit 11 bit 10 C10 R/W bit 2 C02 R/W bit 10 bit 9 C09 R/W bit 1 C01 R/W bit 9 OTDI R/W bit 1 bit 8 C08 R/W bit 0 C00 R/W bit 8 OTD0 R/W bit 0 Initial value 0000--00B Initial value ---00000B Initial value XXXXXXXXB Initial value XXXXXXXXB
* Lower compare register channel 0 to channel 3 (OCCP0 to OCCP3) bit 7 bit 6 bit 5 OCCP0 : 000050H OCCP1 : 000052H C07 C06 C05 OCCP2 : 000054H OCCP3 : 000056H R/W R/W R/W * Compare control status register channel 0 to channel 3 (OCS0 to OCS3) bit 15 OCS1 : 000059H OCS3 : 00005BH -- -- bit 7 OCS0 : 000058H OCS2 : 00005AH ICP1 R/W bit 14 -- -- bit 6 ICP0 R/W bit 13 -- -- bit 5 ICE1 R/W
CMOD OTE1 OTE0 R/W bit 4 ICE0 R/W R/W bit 3 -- -- R/W bit 2 -- --
CST1 CST0 R/W R/W
R/W : Readable and writable -- : Unused X : Indeterminate
56
To Top / Lineup / Index
MB90650A Series
* Block diagram
16-bit timer/counter value (T15 to T00)
OUT0 (OUT2)
Compare control
TQ
OTEO
Compare register 0 (2) CMOD
Internal data bus
16-bit timer/counter value (T15 to T00)
OUT1 (OUT3)
Compare control
TQ
OTE1
Compare register 1 (3) ICP1 Controller Control blocks ICP0 ICE1 ICE0 Compare 1 interrupt (3) Compare 0 interrupt (2)
57
To Top / Lineup / Index
MB90650A Series
(3) Input Capture The input capture consists of two independent external input pins, their corresponding capture registers, and a control register. The value of the 16-bit free-run timer can be stored in the capture register and an interrupt generated when the specified edge is detected on the signal from the external input pin. * The edge to detect on the external input signal is selectable. Detection of rising edges, falling edges, or either edge can be specified. * The two input capture channels can operate independently. * An interrupt can be generated on detection of the specified edge on the external input signal. The input capture interrupt can activate the intelligent I/O service. * Register details
* Input capture register channel 0, channel 1 (IPCP0, IPCP1) bit 15 IPCP0 : 000061H IPCP1 : 000063H CP15 R bit 7 IPCP0 : 000060H IPCP1 : 000062H CP07 R * Input capture control status register (ICS0, 1) bit 7 000064H ICP1 R/W R/W : Readable and writable R : Read only X : Indeterminate bit 6 ICP0 R/W bit 5 ICE1 R/W bit 4 ICE0 R/W bit 3 bit 2 bit 1 bit 0 Initial value 00000000B bit 14 CP14 R bit 13 CP13 R bit 6 CP06 R bit 12 CP12 R bit 5 CP05 R bit 11 CP11 R bit 4 CP04 R bit 10 CP10 R bit 3 CP03 R bit 2 CP02 R bit 9 CP09 R bit 1 CP01 R bit 8 CP08 R bit 0 CP00 R Initial value XXXXXXXXB Initial value XXXXXXXXB
EG11 EG10 EG01 EG00 R/W R/W R/W R/W
The 16-bit free-run timer value is stored in these registers when the specified edge is detected on the input waveform from the corresponding external pin. (Always use word access. Writing is prohibited.) * Block diagram
Capture data register 0
Edge detection
IN0
Internal data bus
16-bit timer/counter value (T15 to T00)
EG11 EG10 EG01 EG00
Capture data register 1
Edge detection
IN1
ICP1
ICP0
ICE1
ICE0 Interrupt Interrupt
58
To Top / Lineup / Index
MB90650A Series
11. Watchdog Timer, Timebase Timer, and Watch Timer The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase timer or the 15-bit watch timer as aclock source, a control register, and a watchdog reset controller. The timebase timer consists of an 18-bit timer and a circuit that controls interval interrupts. Note that the timebase timer uses the main clock, regardless of the setting of the MCS bit and SCS bit in CKSCR. The watch timer consists of a 15-bit timer and a circuit that controls interval interrupts. Note that the watch timer uses the sub clock, regardless of the setting of the MCS bit SCS bit in CKSCR. (1) Register Configuration
* Watchdog timer control register (WDTC) bit 7 Address : 0000A8H PONR R * Timebase timer control register (TBTC) bit 15 Address : 0000A9H Reserved -- * Watch timer control register (WTC) bit 7 Address : 0000AAH bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value bit 14 -- -- bit 13 -- -- bit 12 TBIE R/W bit 11 TBOF R/W bit 10 TBR W bit 9 bit 8 Initial value 1--00000B bit 6 -- -- bit 5 bit 4 bit 3 bit 2 WTE W bit 1 WT1 W bit 0 WT0 W Initial value XXXXX111B
WRST ERST SRST R R R
TBC1 TBC0 R/W R/W
WDCS SCE R/W R
WTIE WTOF WTR WTC2 WTC1 WTC0 1 X 0 0 0 0 0 0 B R/W R/W R R/W R/W R/W
R/W : R: W: --: X:
Readable and writable Read only Write only Unused Indeterminate
59
To Top / Lineup / Index
MB90650A Series
(2) Block Diagram
Main clock TBTC TBC1 TBC0 TBR TBIE TBOF Timebase interrupt WDTC WT1 Selector WT0 WTE Internal data bus 2-bit counter OF CLR Watchdog reset generator CLR WDGRST To internal reset generator AND Q S R Selector 212 214 216 219 TBTRES Clock input Timebase timer 212 214 216 219
WTC AND WDCS SCE WTC1 WTC0 WTR WTIE WTOF Timer interrupt AND Q S R S QR Selector 210 213 214 215 WTRES Sub clock SCM Power-on reset sub clock stops 210 213 214 215
Watch timer Clock input
WDTC PONR N WRST ERST SRST RST pin From RST bit in the STBYC register From power-on generation
60
To Top / Lineup / Index
MB90650A Series
12. I2C Interface The I2C interface is a serial I/O port that supports the Inter-IC bus and operates as a master/slave device on the I2C bus. This module has the following features: * * * * * * * Master/slave transmission/reception Arbitration function Clock synchronization function Slave address/general call address detection function Transfer direction detection function Start condition repeat generation and detection function Bus error detection function
(1) Register Configuration
* I2C bus status register (IBSR) bit 7 Address : 000080H BB R * I2C bus control register (IBCR) bit 15 Address : 000081H BER R/W * I2C bus clock control register (ICCR) bit 7 Address : 000082H -- -- * I2C bus address register (IADR) bit 15 Address : 000083H -- -- * I2C bus data register (IDAR) bit 7 Address : 000084H D7 R/W bit 6 D6 R/W bit 5 D5 R/W bit 4 D4 R/W bit 3 D3 R/W bit 2 D2 R/W bit 1 D1 R/W bit 0 D0 R/W Initial value XXXXXXXXB bit 14 A6 R/W bit 13 A5 R/W bit 12 A4 R/W bit 11 A3 R/W bit 10 A2 R/W bit 9 A1 R/W bit 8 A0 R/W Initial value -XXXXXXXB bit 6 -- -- bit 5 EN R/W bit 4 CS4 R/W bit 3 CS3 R/W bit 2 CS2 R/W bit 1 CS1 R/W bit 0 CS0 R/W Initial value --0XXXXXB bit 14 BEIE R/W bit 13 SCC R/W bit 12 MSS R/W bit 11 ACK R/W bit 10 bit 9 bit 8 INT R/W Initial value 00000000B bit 6 RSC R bit 5 AL R bit 4 LRB R bit 3 TRX R bit 2 AAS R bit 1 GCA R bit 0 FBT R Initial value 00000000B
GCAA INTE R/W R/W
R/W R -- X
: : : :
Readable and writable Read only Unused Indeterminate
61
To Top / Lineup / Index
MB90650A Series
(2) Block Diagram
ICCR EN Clock divider 1 ICCR CS4 CS3 CS2 CS1 CS0 IBSR BB RSC LRB TRX FBT AL Internal data bus IBCR BER SCL BEIE Interrupt request INTE INT IBCR SCC MSS ACK GCAA Start Master ACK enable GC-ACK enable Start/stop condition generation End IRQ SDA Bus busy Repeat start Last bit Transmit/receive First byte Arbitration lost detection Start/stop condition generation Error 248 Clock selection 1 Clock divider 2 16 32 64 128 256 5 6 7 8 Peripheral clock I2C enable
Sync Shift clock generation
Clock selection 2 Shift clock edge change timing
IDAR IBSR Slave AAS GCA Global call Slave address comparison
IADR
62
To Top / Lineup / Index
MB90650A Series
13. External Bus Pin Control Circuit The external bus pin control circuit controls the external bus pins required to extend the CPU's address/data bus outside the device. (1) Register Configuration
* Auto-ready function selection register (ARSR) bit 15 Address : 0000A5H ICR1 W * External address output control register (HACR) bit 7 Address : 0000A6H E23 W * Bus control signal selection register (ECSR) bit 15 Address : 0000A7H CKE W bit 14 RYE W bit 13 HDE W bit 12 bit 11 bit 10 bit 9 LMBS W bit 8 -- -- Initial value 0000*00-B bit 6 E22 W bit 5 E21 W bit 4 E20 W bit 3 E19 W bit 2 E18 W bit 1 E17 W bit 0 E16 W Initial value 00000000B bit 14 bit 13 bit 12 bit 11 -- -- bit 10 -- -- bit 9 bit 8 Initial value 0011--00B
ICR0 HMR1 HMR0 W W W
LMR1 LMR0 W W
ICBS HMBS WRE W W W
W : Write only -- : Unused * : "1" or "0"
(2) Block Diagram
P0 P0 data
P1
P2
P3 P3 P0
P0 direction
RB
Data control
Address control
Access control
Access control
63
To Top / Lineup / Index
MB90650A Series
14. Low-power Consumption Mode (CPU Intermittent Operation Function, Oscillation Stabilization Delay Time, Clock Multiplier Function) The following are the operating modes: PLL clock mode, PLL sleep mode, PLL watch mode, pseudo-watch mode, main clock mode, main sleep mode, main watch mode, main stop mode, sub clock mode, sub sleep mode, sub watch mode, and sub stop mode. Aside from the PLL clock mode, all of the other operating modes are low-power consumption modes. In main clock mode and main sleep mode, the main clock (main OSC oscillation clock) and the sub clock (sub OSC oscillation clock) operate. In these modes, the main clock divided by 2 is used as the operation clock, the sub clock (sub OSC oscillation clock) is used as the timer clock, and the PLL clock (VCO oscillation clock) is stopped. In sub clock mode and sub sleep mode, only the sub clock operates. In these modes, the sub clock is used as the operation clock, and the main clock and PLL clock are stopped. In PLL sleep mode and main sleep mode, only the CPU's operation clock is stopped; all clocks other than the CPU clock operate. In pseudo-watch mode, only the watch timer and timebase timer operate. In PLL watch mode, main watch mode, and sub watch mode, only the watch timer operates. In this mode, only the sub clock is used for operation, while the main clock and the PLL clock are stopped (the difference between the PLL watch mode, the main watch mode and the sub watch mode is that it resumes operation after an interrupt in the PLL clock mode, the main clock mode, and the sub clock mode respectively, and there is no reference concerning about clock mode operation). The main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to retain data while consuming the least amount of power. (The difference between the main stop mode and the sub stop mode is that it resumes operation in the main clock mode and the sub clock mode respectively, and there is no reference concerning about stop mode operation). The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing registers, on-chip memory, on-chip resources, and the external bus. Processing is possible with lower power consumption by reducing the execution speed of the CPU while supplying a high-speed clock and using on-chip resources. The PLL clock multiplier can be selected as either 2, 4, 6, or 8 by setting the CS1 and CS0 bits. These clocks are divided by 2 to be used as a machine clock. The WS1 and WS0 bits can be used to set the main clock oscillation stabilization delay time for when stop mode is woken up.
64
To Top / Lineup / Index
MB90650A Series
(1) Register Configuration
* Low-power consumption mode control register (LPMCR) bit 7 Address : 0000A0H STP W * Clock selection register (CKSCR) bit 15 Address : 0000A1H SCM R bit 14 MCM R bit 13 WS1 R/W bit 12 WS0 R/W bit 11 SCS R/W bit 10 MCS R/W bit 9 CS1 R/W bit 8 CS0 R/W Initial value 11111100B bit 6 SLP W bit 5 SPL R/W bit 4 RST W bit 3 TMD W bit 2 CG1 R/W bit 1 CG0 R/W bit 0 -- Initial value 00011000B
R/W R W --
: : : :
Readable and writable Read only Write only Unused
65
To Top / Lineup / Index
MB90650A Series
(2) Block Diagram * Low-power consumption control circuit and clock generator
CKSCR SCM SCS Sub clock switching control Sub clock divided by 4 (OSC oscillation)
CKSCR MCM MCS CKSCR CS1 CS0 CPU Clock selector 1/2 S PLL multiplier circuit 1 2 3 4 CPU system clock generation Main clock (OSC oscillation) CPU clock
0/9/17/33 intermittent cycle selection
LPMCR CG1 CG0 Internal data bus CPU intermittent operation function Cycle count selection circuit Peripheral clock generation SCM SLEEP Standby controller RST cancel MSTP STOP Main OSC stop Sub OSC stop Peripheral clock
LPMCR SLP STP TMD
Interrupt request or RST CKSCR WS1 WS0 LPMCR SPL LPMCR RST Pin high-impedance controller Oscillation stabilization delay time selector 24 213 215 218 Clock input Timebase timer 212 214 216 219 Pin Hi-Z RST pin Internal RST To watchdog timer WDGRST
Internal reset generator
66
To Top / Lineup / Index
MB90650A Series
* State transition diagram for clock selection (1)
Power-on
Main SCS = 1, MCS = 1 <1> SCM = 1, MCM = 1 CS1/0 = xx
Main PLLx SCS = 1, MSC = 0 SCM = 1, MCM = 1 CS1/0 = xx
<2>
<3> <7> PLL1 Main SCS = 0 or MCS = 0 SCM = 1, MCM = 0 <7> CS1/0 = 00
PLL 1 multiplier SCS = 1, MSC = 0 <6> SCM = 1, MCM = 0 CS1/0 = 00
<4>
<7> Sub PLLx SCS = 1, MCS = 0 SCM = 0, MCM = 1 <9> CS1/0 = xx PLL2 Main SCS = 0 or MCS = 1 SCM = 1, MCM = 0 <6> CS1/0 = 01
PLL 2 multiplier SCS = 1, MSC = 0 SCM = 1, MCM = 0 CS1/0 = 01
<8>
<7> PLL3 Main SCS = 0 or MCS = 1 SCM = 1, MCM = 0 CS1/0 = 10 <8>
<5> PLL 3 multiplier SCS = 1, MSC = 0 SCM = 1, MCM = 0 <6> CS1/0 = 10
<8> Main Sub SCS = 0, MCS = x MCM = 1 SCM = 1 PLL4 Main SCS = 0 or MCS = 1 SCM = 1, MCM = 0 CS1/0 = 11 PLL 4 multiplier SCS = 1, MSC = 0 SCM = 1, MCM = 0 CS1/0 = 11
<8>
<6>
<1> MCS bit cleared and SCS bit set <2> PLL clock oscillation stabilization delay complete and CS1/0 = 00 <3> PLL clock oscillation stabilization delay complete and CS1/0 = 01 <4> PLL clock oscillation stabilization delay complete and CS1/0 = 10 <5> PLL clock oscillation stabilization delay complete and CS1/0 = 11 <6> MCS bit set or SCS bit cleared <7> PLL clock and main clock synchronized timing and SCS = 1 <8> PLL clock and main clock synchronized timing and SCS = 0 <9> Main clock oscillation stabilization delay complete and MCS = 0
67
To Top / Lineup / Index
MB90650A Series
* State transition diagam for clock selection (2)
Power-on
<1> Main SCS = 1, MCS = 1 SCM = 1 MCM = 1 <4> PLLx Sub SCS = 0, MCS = x SCM = 1, MCM = 0 CS1/0 = xx <5>
Main Sub SCS = 0 SCM = 1 MCM = 1
<2>
Sub Main SCS = 1 SCM = 0 MCM = 1
<3>
Sub SCS = 0 SCM = 0 MCM = 1
Main PLLx SCS = 1, MCS = 0 SCM = 1, MCM = 1 CS1/0 = xx
<6>
<1> SCS bit cleared <2> Sub clock edge detection timing <3> SCS bit set <4> Main clock oscillation stabilization delay complete and MCS = 1 <5> PLL clock and main clock synchronized timing and SCS = 0 <6> Main clock ascillation stabilization delay complete and MCS = 0
68
To Top / Lineup / Index
MB90650A Series
15. Delayed Interrupt Generation Module The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to the F2MC-16L CPU can be generated and cleared by software using this module. (1) Register Details
* Delayed interrupt generation /release register (DIRR) bit 15 Address : 00009FH -- bit 14 -- bit 13 -- bit 12 -- bit 11 -- bit 10 -- bit 9 -- bit 8 R0 R/W R/W : Readable and writable -- : Unused Initial value -------0B
The DIRR register controls generation and clearing of delayed interrupt requests. Writing "1" to the register generates a delayed interrupt request. Writing "0" to the register clears the delayed interrupt request. The register is set to the interrupt cleared state by a reset. Either "0" or "1" can be written to the reserved bits. However, considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for register access. (2) Block Diagram
Internal data bus
Delayed interrupt generation/release decoder
Interrupt latch
69
To Top / Lineup / Index
MB90650A Series
16. DTMF Generator The DTMF (dual tone multifrequency) generator is a module that can generate a series of audio tones as heard from a push-button telephone or a radio transceiver with a keypad. It has the following features: Capable of generating DTMF tones continuously (or even a single tone) Capable of generating all CCITT tones: 0 to 9, *, #, A to D (1) Register list
* DTMF control register (DTMC) Address : 000088H bit 7 -- -- * DTMF data register (DTMD) Address : 000089H bit 15 -- -- R/W : Read/write enabled -- : Unused X : Undefined bit 6 CSL2 R/W bit 14 -- -- bit 5 CSL1 R/W bit 13 -- -- bit 4 CSL0 R/W bit 12 -- -- bit 3 CDIS R/W bit 11 bit 2 bit 1 bit 0 -- -- bit 8 Initial value 000X0000B Initial value 00000000B
RDIS OUTE R/W bit 10 R/W bit 9
DDAT3 DDAT2 DDAT1 DDAT0 R/W R/W R/W R/W
(2) Block diagram
Clock pulse Frequency divider Frequency select COL staircase generator Voltage data
DTMF ROW/COL decoder Frequency select Preset counter Count clock Terminate Internal clock Frequency divider ROW staircase generator
Adder
Control signal generator
Frequency select
DTMF data register (DTMD)
DTMF control register (DTMC)
Internal bus
70
To Top / Lineup / Index
MB90650A Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V) Parameter Symbol VCC1 VCC2 VCC
(VCC1 = VCC2)
Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Max. VSS + 4.0 VSS + 7.0 VSS + 7.0 VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 7.0 10 15 3 4 60 100 30 50 -10 -15
Unit V V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA
Remarks MB90652A/653A/654A, MB90F654A MB90P653A MB90652A/653A/654A, MB90F654A *1 MB90P653A *1 MB90652A/653A/654A, MB90F654A MB90P653A MB90652A/653A/654A, MB90F654A MB90P653A MB90652A/653A/654A, MB90F654A *2 MB90P653A *2,*6 MB90652A/653A/654A, MB90F654A *2 MB90P653A *2,*6 MB90652A/653A/654A, MB90F654A *3 MB90P653A *3 MB90652A/653A/654A, MB90F654A *4 MB90P653A *4 MB90652A/653A/654A, MB90F654A MB90P653A MB90652A/653A/654A, MB90F654A *5 MB90P653A *5 MB90652A/653A/654A, MB90F654A *3 MB90P653A *3
AVCC Power supply voltage AVRH AVRL
VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3
DVRH
Input voltage
VI
VSS - 0.3 VSS - 0.3
Output voltage
VO
VSS - 0.3 VSS - 0.3
"L" level maximum output current
IOL
-- --
"L" level average output current
IOLAV
-- --
"L" level total maximum output current "L" level total average output current "H" level maximum output current
IOL
-- --
IOLAV
-- --
IOH
-- --
(Continued)
71
To Top / Lineup / Index
MB90650A Series
(Continued)
(VSS = AVSS = 0.0 V) Parameter "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature Symbol Value Min. -- -- IOH IOHAV PD TA Tstg -- -- -- -- -40 -55 Max. -3 -4 -60 -100 -30 200 +85 +150 Unit mA mA mA mA mA mW C C Remarks MB90652A/653A/654A, MB90F654A *4 MB90P653A MB90652A/653A/654A, MB90F654A MB90P653A *5 *4
IOHAV
*1: AVCC, AVRH, AVRL and DVRH must not exceed VCC (VCC1 and VCC2 are contained) . Similarly, AVRL must not exceed AVRH. *2: VI and VO must not exceed VCC (VCC1 and VCC2 are contained) + 0.3 V. *3: Maximum output current specifies the peak value or one corresponding pin. *4: The average output current is the rating for the current from an individual pin averaged over 100 ms. *5: The average total output current is the rating for the current from all pins averaged over 100 ms. *6: Applies to the P47 and P70 to P72 on the MB90652A/653A/654A and MB90F654A. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
72
To Top / Lineup / Index
MB90650A Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Symbol Value Min. 2.2 VCC1 2.7 2.4 2.2 VCC2 2.7 2.4 Power supply voltage VCC1 1.8 1.8 1.8 1.8 VCC2 1.8 1.8 VIH "H" level input voltage VIHS VIHM VIHT VIL "L" level input voltage VILS VILM VILT Operating temperature TA 0.7 VCC 0.8 VCC VCC - 0.3 2.4 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -40 Max. 3.6 3.6 3.6 5.5 5.5 5.5 3.6 5.5 3.6 5.5 5.5 5.5 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VSS + 0.3 0.8 +85 Unit V V V V V V V V V V V V V V V V V V V V C Remarks For normal operation (MB90652A/653A/654A) For normal operation (MB90P653A) For normal operation (MB90F654A) For normal operation (MB90652A/653A/654A) For normal operation (MB90P653A) For normal operation (MB90F654A) To maintain statuses in stop mode (MB90652A/653A/654A) To maintain statuses in stop mode (MB90P653A) To maintain statuses in stop mode (MB90F654A) To maintain statuses in stop mode (MB90652A/653A/654A) To maintain statuses in stop mode (MB90P653A) To maintain statuses in stop mode (MB90F654A) Pins other than VIHS and VIHM Hysteresis input pins MD pin input TTL input pins PIns other than VILS and VILM Hysteresis input pins MD pin input TTL input pins
Note: I2C must be used at above 2.7 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
73
To Top / Lineup / Index
MB90650A Series
3. DC Characteristics
(MB90652A/653A/654A: VCC = 2.2 V to 3.6 V, VSS = 0.0 V, TA = -40C to +85C) (MB90P653A: VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) (MB92F654A: VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Typ. Max. VOH VCC2 = 4.5 V, Pins except IOH = -4.0 mA P47, P70 to P72 VCC = 2.7 V, IOH = -1.6 mA All output pins VCC2 = 4.5 V, IOL = 4.0 mA VCC = 2.7 V, IOL = 2.0 mA VCC2- 0.5 VCC1- 0.3 -- -- -10 40 20 -- -- When VCC = 3.0 V Internal 8 MHz operation -- -- -- -- When VCC = 3.0 V Internal 8 MHz operation -- -- -- -- -- -- -- -- 80 65 0.1 10 17 19 2.5 20 24 26 4.2 -- -- 0.4 0.4 10 400 200 10 20 24 26 5 27 31 33 10 V V V V A k MB90P653A k A mA mA mA mA mA mA mA mA MB90652A/653A/654A: During normal operation MB90652A/653A/654A: In A/D operation MB90652A/653A/654A: In D/A operation MB90652A/653A/654A: During sleep MB90P653A: During normal operation MB90P653A: In A/D operation MB90P653A: In D/A operation MB90P653A: During sleep MB90652A/653A/654A, MB90F654A When the 5-V power supply is used When the 3-V power supply is used *1 When the 5-V power supply is used When the 3-V power supply is used
Parameter "H" level output voltage*2
"L" level output VOL voltage*2 Input leakage IIL current Pull-up resistor RPULL Open-drain output leakage Ileak current ICC ICC
Except P50 VCC = 3.3 V, to P57, VSS < VI < VCC P90, P91 -- P40 to P47, P70 to P72 When VCC = 3.0 V, TA = +25C --
-- ICC Power supply current ICCS ICC ICC -- ICC ICCS
* 1 : P40 to P46 are N-ch open-drain pins to be controlled and are usually used as CMOS devices. * 2 : When the device is used with dual power supplies, the P20 to P27, P30 to P37, P40 to P47, and P70 to P72 are the 5 V pins and the rest are the 3 V pins.
(Continued)
74
To Top / Lineup / Index
MB90650A Series
(Continued)
(MB90652A/653A/654A: VCC = 2.2 V to 3.6 V, VSS = 0.0 V, TA = -40C to +85C) (MB90P653A: VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) (MB90F654A: VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Typ. Max. -- -- -- When VCC = 3.0 V Internal 16 MHz operation -- -- -- When VCC = 3.0 V Internal 16 MHz operation -- -- -- -- -- 20 27 33 31 34 4.8 6.2 0.1 0.2 16 35 45 50 41 42 10 12 20 40 140 mA mA mA mA mA mA mA A A MB90652A/653A/654A: During normal operation MB90F654A: During normal operation MB90F654A: Flash write/erase MB90652A/653A/654A: In A/D operation MB90652A/653A/654A: In D/A operation MB90652A/653A/654A: During sleep MB90F654A: During sleep MB90652A/653A/654A: During stop MB90F654A: During stop
Parameter
Symbol
ICC ICC ICC ICC ICC ICCS -- ICCS Power supply current ICCH -- ICCH ICCL -- ICCL ICCT ICCT ICCT Input capacitance CIN Except AVCC, AVSS, VCC, VSS -- -- VCC = 3.0 V, TA = +25C External 32 kHz operation
TA = +25C When VCC = 3.0 V VCC = 3.0 V, TA = +25C External 32 kHz operation (Internal 8 MHz operation)
MB90652A/653A/654A, A MB90F654A: In sub operation mA A A A pF MB90P653A: In sub operation MB90652A/653A/654A: In watch mode MB90F654A: In watch mode MB90P653A: In watch mode
-- -- -- -- --
4.4 10 15 15 10
6 30 30 60 80
Note: VCC = VCC1 = VCC2
75
To Top / Lineup / Index
MB90650A Series
4. AC Characteristics
(1) Clock Timing (VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Min. Typ. Max. 3 3 -- 31.25 62.5 -- 5 10 -- -- 1.5 1.5 -- 62.5 -- -- -- -- 32.768 -- -- 30.5 -- -- 15.2 -- -- -- 8.192 -- 122.1 -- 32 16 -- 333 333 -- -- -- -- 5 16 8 -- 666 -- 5 MHz MB90652A/653A/ 654A,MB90F654A
Parameter
Symbol
Pin name
Condition -- --
Clock frequency
FCH FCL tC tCL
X0, X1 X0A, X1A X0, X1 X0A, X1A X0
MHz MB90P653A kHz ns ns s ns ns s ns MHz External clock MB90652A/653A/ 654A,MB90F654A MB90652A/653A/ 654A,MB90F654A *2 MB90P653A *2 *2 MB90652A/653A/ 654A,MB90F654A MB90P653A
-- -- -- -- -- --
Clock cycle time
PWH PWL Input clock pulse width PWLH PWLL Input clock rise tcr time and fall time tcf Internal operating clock frequency Internal operating clock cycle time Frequency fluctuation ratio fCP fCPL tCP tCPL f
X0A X0
-- -- -- --
-- -- -- -- --
MHz MB90P653A kHz ns s % When locked *1
-- -- -- --
*1: The frequency fluction ratio indicates the maximum fluctuation ratio from the set center frequency while locked when using the PLL multiplier.
+ fO + x 100 (%) Center frequency fO - -
f =
Because the PLL frequency fluctuates around the set frequency with a certain cycle [approximately CLK x (1 CYC to 50 CYC)], the worst value is not maintained for long. (The pulse, if featured with the long period, would produce practically no error.) *2: The duty ratio should be in the range 30% to 70%. Note: VCC = VCC1 = VCC2 76
To Top / Lineup / Index
MB90650A Series
*Main clock timing condition (X0, X1)
tC 0.8 VCC X0 PWH tcf PWL tcr 0.2 VCC
* Subclock timing condition (X0A, X1A )
tCL 0.8 VCC X0A PWHL PWLL 0.2 VCC
77
To Top / Lineup / Index
MB90650A Series
* PLL operation assurance range
Relationship between the internal operating clock frequency and power supply voltage (MB90652A/653A/654A, MB90F654A) (V) Normal operation range Power supply voltage (VCC) 3.6 PLL operation assurance range 2.7 2.5 2.2
1
3
5 Internal clock (fCP)
16
(MHz)
Relationship between the internal oprating clock frequency and power supply voltage (MB90P653A) (V) Normal operation range Power supply voltage (VCC) 3.6 PLL operation assurance range 2.7
1.5
3 Internal clock (fCP)
8
(MHz)
Relationship between the oscillation frequency and internal operating clock frequency (MHz) 16 Multiply Multiply by 4 by 3 Multiply by 2 Multiply by 1 No multiplier
12 Internal clock (fCP) 9 8
4
34
8
16 Oscillation clock (FC)
24
32
(MHz)
78
To Top / Lineup / Index
MB90650A Series
The AC characteristics are for the following measurement reference voltages. * Input signal waveform
Hysteresis input pins 0.8 VCC 0.2 VCC
* Output signal waveform
Output pins 2.4 V 0.2 V
Other than hysteresis or MD input pins 0.7 VCC 0.3 VCC
79
To Top / Lineup / Index
MB90650A Series
(2) Clock Output Timing (VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- VCC = 3.0 V 10% tCP -- ns ns ns In the external frequency of 5 MHz tCP / 2 - 20 tCP / 2 + 20 CLK CLK tCHCL CLK tCP / 2 - 64 tCP / 2 + 64
Parameter Cycle time
Pin Symbol name tCYC CLK
tCP: See "(1) Clock Timing." Note: VCC = VCC1 = VCC2
tCYC tCHCL 2.4 V CLK 0.8 V 2.4 V
(3) Reset Input Specifications Pin name RST (VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- 16 tCP -- ns
Parameter Reset input time tCP: See "(1) Clock Timing." Note: VCC = VCC1 = VCC2
Symbol tRSTL
t RSTL
RST 0.2 VCC 0.2 VCC
* AC characteristics measurement conditions
Pin CL : Load capacitance at testing
CL
CLK, ALE: CL = 30 pF AD15 to AD00 (address/data bus), RD, WR: CL = 80 pF
80
To Top / Lineup / Index
MB90650A Series
(4) Power on Supply Specifications (Power-on Reset) (VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- -- -- 1 30 -- ms ms * Due to repeat operation
Parameter Power supply rising time Power supply cut-off time
Symbol tR tOFF
Pin name VCC VCC
* : When the power rising, VCC must be less than 0.2 V. Notes: * The above standards are the values needed in order to activate a power-on reset. * Activate a power-on reset by turning on the power supply again this in device. * VCC = VCC1 = VCC2
tR VCC 2.7 V 0.2 V tOFF
Abrupt changes in the power supply voltage may cause a power-on reset. When changing the power supply voltage during operation, suppress variations in the voltage and ensure that the voltage rises smoothly, as shown in the following figure.
Main power supply voltage VCC Sub-power supply voltage Holding RAM data VSS
It is recommended that the rate of increase in the voltage be kept to no more than 50 mV/ms.
81
To Top / Lineup / Index
MB90650A Series
(5) Bus Read Timing (VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- tCP /2 - 20 tCP / 2 - 35 tCP / 2 - 25 tCP / 2 - 40 tCP / 2 - 15 tCP - 15 -- -- 3 tCP / 2 - 20 -- -- 0 tCP / 2 - 15 tCP / 2 - 10 tCP / 2 -20 tCP / 2 - 20 -- -- -- -- -- -- 5 tCP / 2 - 60 5 tCP / 2 - 80 -- 5 tCP / 2 - 60 5 tCP / 2 - 80 -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MASK/FLASH MB90P653A MASK/FLASH MB90P653A MASK/FLASH MB90P653A MASK/FLASH MB90P653A
Parameter ALE pulse width
Symbol tLHLL
Pin name ALE Multiplexed address Multiplexed address Multiplexed address Multiplexed address RD D15 to D00 D15 to D00 RD, ALE Address, RD Address, CLK RD, CLK
Valid address ALE time tAVLL ALE address valid time Valid address RD time Valid address valid data input RD pulse width RD valid data input RD data hold time RD ALE time RD address valid time tLLAX tAVRL tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX
Valid address CLK time tAVCH RD CLK time tCP: See "(1) Clock Timing." Note: VCC = VCC1 = VCC2 tRLCH
82
To Top / Lineup / Index
MB90650A Series
tAVCH CLK 2.4 V
tRLCH 2.4 V
tAVLL ALE 2.4 V 2.4 V
tLLAX 0.8 V tAVRL tRLRH
tRHLH 2.4 V
tLHLL
RD
2.4 V 0.8 V tRHAX
A23 to A16
2.4 V 0.8 V tRLDV tAVDV
2.4 V 0.8 V tRHDX 2.4 V 0.8 V 0.7 VCC 0.3 VCC Read data 0.7 VCC 0.3 VCC
D15 to D00
2.4 V 0.8 V
Address
83
To Top / Lineup / Index
MB90650A Series
(6) Bus Write Timing (VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Pin name Condition A23 to A00 WR D15 to D00 D15 to D00 A23 to A00 WR, ALE WR, ALE -- -- -- -- -- -- -- Value Min. tCP - 15 3 tCP / 2 - 20 3 tCP / 2 - 20 20 30 tCP / 2 - 10 tCP / 2 - 15 tCP / 2 - 20 Max. -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns MASK/FLASH MB90P653A Remarks
Valid address WR time tAVWL WR pulse width Valid data output WR time WR data hold time tWLWH tDVWH tWHDX
WR address valid time tWHAX WR ALE time WR CLK time tCP: See "(1) Clock Timing." Note: VCC = VCC1 = VCC2 tWHLH tWLCH
tWLCH CLK 2.4 V
tWHLH ALE 2.4 V
tAVWL
tWLWH 2.4 V 0.8 V tWHAX
WR (WRL, WRH)
A23 to A16
2.4 V 0.8 V tDVWH
2.4 V 0.8 V tWHDX Write data 2.4 V 0.8 V
D15 to D00
2.4 V 0.8 V Address
2.4 V 0.8 V
84
To Top / Lineup / Index
MB90650A Series
(7) Ready Input Timing (VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- -- -- 45 70 0 -- -- -- ns ns ns MASK/FLASH MB90P653A
Parameter RDY setup time RDY hold time
Symbol tRYHS tRYHH
Pin name RDY RDY
Notes: * Use the auto-ready function if the RDY setup time is too short * VCC = VCC1 = VCC2.
CLK ALE
2.4 V
2.4 V
RD/WR
RDY (When wait states are not inserted)
tRYHS 0.8 VCC
tRYHH 0.8 VCC
RDY (When one wait states are inserted)
0.2 VCC
0.2 VCC tRYHS
85
To Top / Lineup / Index
MB90650A Series
(8) Hold Timing (VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- -- 30 tCP tCP 2 tCP ns ns
Parameter Pin floating HAK time HAK pin valid time tCP: See "(1) Clock Timing."
Symbol tXHAL tHAHV
Pin name HAK HAK
Notes: * After reading HRQ, more than one cycle is required before changing HAK. * VCC = VCC1 = VCC 2
HAK tXHAL Pin
2.4 V 0.8 V tHAHV High impedance
86
To Top / Lineup / Index
MB90650A Series
(9) UART Timing (VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. 8 tCP -80 CL = 80 pF + 1 TTL for the internal shift clock mode output pin -120 100 200 tCP 4 tCP 4 tCP CL = 80 pF + 1 TTL for the external shift clock mode output pin -- -- 60 120 60 120 -- 80 120 -- -- -- -- -- 150 200 -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns MASK/FLASH MB90P653A MASK/FLASH MB90P653A MASK/FLASH MB90P653A MASK/FLASH MB90P653A MASK/FLASH MB90P653A
Parameter Serial clock cycle time
Symbol tSCYC
Pin name -- -- -- -- -- -- -- -- --
SCK SOT delay time tSLOV Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width tIVSH tSHIX tSHSL tSLSH
SCK SOT delay time tSLOV Valid SIN SCK SCK valid SIN hold time tIVSH tSHIX
Notes: * These are the AC characteristics for CLK synchronous mode. * CL is the load capacitance connected to the pin at testing. * tCP is the machine cycle period (unit: ns). * VCC = VCC1 = VCC 2
87
To Top / Lineup / Index
MB90650A Series
* Internal shift clock mode
tSCYC SCK 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 2.4 V 0.8 V
* External shift clock mode
tSLSH SCK 0.2 VCC tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC tSHSL 0.8 VCC
88
To Top / Lineup / Index
MB90650A Series
(10) I/O Extended Serial Timing (VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. 8 tCP CL = 80 pF + 1 TTL for the internal shift clock mode output pin -- -- tCP tCP 230 460 CL = 80 pF + 1 TTL for the external shift clock mode output pin 230 460 2 tCP tCP 2 tCP -- 80 160 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns MASK/FLASH MB90P653A MASK/FLASH MB90P653A MASK/FLASH MB90P653A
Parameter Serial clock cycle time
Pin Symbol name tSCYC -- -- -- -- -- -- -- -- --
SCK SOT delay time tSLOV Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width Valid SIN SCK SCK valid SIN hold time tIVSH tSHIX tSHSL tSLSH
SCK SOT delay time tSLOV tIVSH tSHIX
Notes: * These are the AC characteristics for CLK synchronous mode. * CL is the load capacitance connected to the pin at testing. * tCP is the machine cycle period (unit: ns). * The values in the table are target values. * VCC = VCC1 = VCC 2
89
To Top / Lineup / Index
MB90650A Series
* Internal shift clock mode
tSCYC SCK 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 2.4 V 0.8 V
* External shift clock mode
tSLSH SCK 0.2 VCC tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.2 VCC 0.8 V CC tSHSL 0.8 VCC
90
To Top / Lineup / Index
MB90650A Series
(11) I2C Timing (VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = -40C to +85C) Parameter SCL clock frequency Symbol fSCL Pin name -- -- Condition -- -- Value Min. 0 4.7 Max. 100 -- Unit kHz s The first clock pulse is generated after this period. Remarks
Bus free time between stop tBUS and start conditions Hold time (re-send) start tHDSTA
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
4.0 4.7 4.0 4.7 0 40 -- -- 4.0
-- -- -- -- -- -- 1000 300 --
s s s s s ns ns ns s
SCL clock L state hold time tLOW SCL clock H state hold time Re-send start condition setup time Data hold time Data setup time tHIGH tSUSTA tHDDAT tSUDAT
SDA and SCL signal rising tR time SDA and SCL signal falling tF time Stop condition setup time Note: VCC = VCC1 = VCC2 tSUSTO
0.8 VCC
SDA
tBUS
0.2 VCC
tLOW tR
tHDSTA tF 0.8 VCC
SCL
0.2 VCC tHDSTA tHDDAT tHIGH tSUDAT
tSUSTA
tSUSTO
91
To Top / Lineup / Index
MB90650A Series
5. A/D Converter Electrical Characteristics
(MB90652A/653A/654A: VCC = 2.2 V to 3.3V, VSS = AVSS =0.0V, 2.7 V AVRH - AVRL, TA = -40C to +85C) (MB90F654A: VCC = 2.4 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V AVRH - AVRL, TA = -40C to +85C) (MB90P653A: VCC = 2.7 V to 3.3 V, VSS = AVSS = 0.0 V, 2.7 V AVRH - AVRL, TA = -40C to +85C) Value Symbol Pin name Unit Remarks Parameter Min. Typ. Max. Resolution Total error Linearity error Differential linearity error Zero transition voltage Full scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Variation between channels IA IAH IR IRH -- IAIN VAIN VOT VFST -- -- -- -- -- -- -- -- -- AN0 to AN7 AN0 to AN7 -- AN0 to AN7 AN0 to AN7 AVRH -- AVRL AVCC AVCC AVRH AVRH AN0 to AN7 -- -- -- -- -- AVRL - 1.5 LSB AVRH - 4.5 LSB 6.125*1 12.25 -- AVRL AVRL + 2.7 0 -- -- -- -- --
*2
10 -- -- -- -- AVRL + 0.5 LSB AVRH - 1.5 LSB -- -- 0.1 -- -- -- 3 -- 200 -- --
10 3.0 2.0 1.9 1.5 AVRL + 2.5 LSB AVRH + 0.5 LSB -- -- 10 AVRH AVCC AVRH - 2.7 -- 5
*3
bit LSB LSB LSB LSB mV mV s s A V V V mA A A A LSB MASK/FLASH MB90P653A MASK/FLASH MB90P653A
-- 5
*3
4
*1: For a 16 MHz machine clock *2: For an 8 MHz machine clock *3: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVRH = 3.0 V). Notes: * The error increases proportionally as |AVRH - AVRL| decreases. * The output impedance of the external circuits connected to the analog inputs should be in the following range. The output impedance of the external circuit should be less than approximately 7 k. When using an external capacitor, it is recommended to have several thousand times the capacitance of the internal capacitor as a guid, if one takes into consideration the effect of the divided capacitance between the external capacitor and the internal capacitor. * If the output impedance of the external circuit is too high, the sampling time might be insufficient (sampling time = 3.75 s @ at a machine clock of 16 MHz). * VCC = VCC1 = VCC2
(Continued)
92
To Top / Lineup / Index
MB90650A Series
(Continued)
* Analog input circuit model diagram
Sample hold circuit Analog input RON1 RON2 RON3 RON4 C1 C0 Comparator
RON1 : RON2 : RON3 : RON4 :
Approx. 5 k Approx. 617 Approx. 617 Approx. 473
C0 : Approx. 35 pF C1 : Approx. 2 pF
Note: Use the values shown as guids only.
93
To Top / Lineup / Index
MB90650A Series
6. D/A Converter Electrical Characteristics
(MB90652A/653A : VCC = 2.2 V to 3.3 V, VSS = DVSS = 0.0 V, 2.2 V DVRH - DVSS, TA = -40C to +85C) (MB90F654A : VCC = 2.4 V to 3.6 V, VSS = DVSS = 0.0 V, 2.4 V DVRH - DVSS, TA = -40C to +85C) (MB90P653A : VCC = 2.7 V to 3.3 V, VSS = DVSS = 0.0 V, 2.7 V DVRH - DVSS, TA = -40C to +85C) Parameter Resolution Differential linearity error Absolute accuracy Linearity error Conversion time Analog reference power supply voltage Reference voltage supply current Analog output impedance *1: *2: *3: *4: Symbol -- -- -- -- -- -- IDVR IDVRS -- DVRH -- Pin name -- -- -- -- -- DVRH Value Min. -- -- -- -- -- 2.2 2.4 2.7 -- -- -- Typ. 8 -- -- -- 10.0 -- -- -- 100 -- 28 Max. 8 0.9 1 1.5 20.0 VCC VCC VCC -- 5 -- Unit bit LSB % LSB s V V V A A k MB90F654A MB90P653A *1 MB90652A/653A/654A*2 *2 *2 *3 *4 Remarks
Conversion time is the value at the load capacitance = 20 pF. DVRH - DVSS (AVSS) Current value at conversion Current value when stopped
Note: VCC = VCC1 = VCC2
94
To Top / Lineup / Index
MB90650A Series
7. DTMF Electrical characteristics
(MB90652A/653A : VCC = 2.2 V to 3.3 V, VSS = DVSS = 0.0 V, 2.2 V DVRH - DVSS, TA = -40C to +85C) (MB90F654A : VCC = 2.4 V to 3.6 V, VSS = DVSS = 0.0 V, 2.4 V DVRH - DVSS, TA = -40C to +85C) (MB90P653A : VCC = 2.7 V to 3.3 V, VSS = DVSS = 0.0 V, 2.7 V DVRH - DVSS, TA = -40C to +85C) Value Symbol Condition Unit Remarks Parameter Min. Typ. Max. Output load condition DTMF output offset voltage (At signal output) DTMF output amplitude (COL single tone) DTMF output amplitude (ROW single tone) COL/ROW level difference Note: VCC =VCC1 = VCC2 RO VMOF VCC = 3 V TA = 25C Machine clock f = 16 MHz 30 k -- -- 0.4 -- -- V To be specified with DTMF pin pull-down resistor
VMFC
450
530
600
mVP-P
When DTMF terminal is opened RO = 200 k
VMFOR RMF
330 1.6
440 2.0
500 2.4
mVP-P dB
* Output level measurement circuit
VCC X0 DTMF X1 VSS RO Audio
Low-pass filter 16MHz
-48 dB / oct
Output level
Analizer
95
To Top / Lineup / Index
MB90650A Series
s EXAMPLE CHARACTERISTICS
(1) "H" Level Output Voltage
VOH vs. IOH VOH (V) 4.0 TA = +25C 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -1 -2 -3 -4 -5 IOH (mA)
(2) "L" Level Output Voltage
VOL vs. IOL VOL (V) 1.0 TA = +25C 0.9 VCC = 3.6 V VCC = 3.3 V VCC = 3.0 V VCC = 2.7 V VCC = 2.5 V VCC = 2.4 V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1 2 3 4 5 IOL (mA) VCC = 2.4 V VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V
(3) "H" Level Input Voltage/"L" Level Input Voltage (COMS Input)
(4) "H" Level Input Voltage/"L" Level Input Voltage (Hysteresis Input)
VIN vs. VCC VIN (V) 2.4 TA = +25C 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 2.4 2.7 3.0 3.3 3.6 VCC (V) VIH VIL VIN (V) 2.4
VIN vs. VCC
TA = +25C 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 2.4 2.7 3.0 3.3
VIHS
VILS
3.6 VCC (V)
VIH: VIL:
Threshold when input voltage is set to "H" level Threshold when input voltage is set to "L" level
VIHS: Threshold when input voltage in hysteresis characteristics is set to "H" level VILS: Threshold when input voltage in hysteresis characteristics is set to "L" level
96
To Top / Lineup / Index
MB90650A Series
(5) Power Supply Current (fCP = Internal Operating Clock Frequency) * Mask ROM products
ICC vs. VCC ICC (mA) 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 2.4 ICCS (mA) 10 TA = +25C fCP = 16 MHZ 9 8 7 6 fCP = 10 MHZ fCP = 8 MHZ fCP = 5 MHZ 5 4 3 2 1 2.7 3 3.3 3.6 VCC (V) 0 2.4 2.7 3 3.3 3.6 VCC (V) fCP = 10 MHZ fCP = 8 MHZ fCP = 5 MHZ fCP = 16 MHZ TA = +25C ICCS vs. VCC
ICCH vs. VCC ICCH (A) 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 2.4 2.7 3 3.3 3.6 VCC (V) TA = +25C ICCL (A) 50 45 40 35 30 25 20 15 10 5 0 2.4 2.7
ICCL vs. VCC
TA = +25C
3
3.3
3.6 VCC (V)
IA vs. AVCC IA (mA) 4.0 TA = +25C 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.4 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.4 IR (mA) 4.0
IR vs. AVCC
TA = +25C
2.7
3
3.3
3.6 AVCC (V)
2.7
3
3.3
3.6 AVCC (V)
97
To Top / Lineup / Index
MB90650A Series
* OTPROM products
ICC vs. VCC ICC (mA) 60 55 50 45 40 35 30 25 20 15 10 5 0 2.4 2.7 3 3.3 3.6 VCC (V) fCP = 10 MHZ fCP = 8 MHZ fCP = 5 MHZ TA = +25C fCP = 16 MHZ ICCS (mA) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2.4
ICCS vs. VCC
TA = +25C
fCP = 16 MHZ
fCP = 10 MHZ fCP = 8 MHZ fCP = 5 MHZ
2.7
3
3.3
3.6 VCC (V)
ICCH vs. VCC ICCH (A) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.4 ICCL (mA) 10 TA = +25C 9 8 7 6 5 4 3 2 1 0 2.7 3 3.3 3.6 VCC (V) 2.4 2.7
ICCL vs. VCC
TA = +25C
3
3.3
3.6 VCC (V)
98
To Top / Lineup / Index
MB90650A Series
* FLAH products
ICC vs. VCC ICC (mA) 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 2.4 TA = +25 C ICCS (mA) 10 fCP = 16 MHZ 9 8 7 fCP = 10 MHZ fCP = 8 MHZ fCP = 5 MHZ 6 5 4 3 2 1 2.7 3 3.3 3.6 VCC (V) 0 2.4 2.7
ICCS vs. VCC TA = +25 C
fCP = 16 MHZ
fCP = 10 MHZ fCP = 8 MHZ fCP = 5 MHZ
3
3.3
3.6 VCC (V)
ICCH vs. VCC ICCH (A) 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 2.4 TA = +25 C ICCL (A) 50 45 40 35 30 25 20 15 10 5 2.7 3 3.3 3.6 VCC (V) 0 2.4 2.7
ICCL vs. VCC TA = +25 C
3
3.3
3.6 VCC (V)
99
To Top / Lineup / Index
MB90650A Series
(6) Pull-up Resistance * Mask ROM products
R vs. VCC R (k) 1000 TA = +25C R (k) 1000 TA = +25C
* OTPROM products
R vs. VCC
100
100
10 2.4
2.7
3
3.3
3.6 VCC (V)
10 2.4
2.7
3
3.3
3.6 VCC (V)
* FLASH products
R -- VCC R (k) 1000
TA = +25 C
100
10 2.4
2.7
3
3.3
3.6 VCC (V)
100
To Top / Lineup / Index
MB90650A Series
s INSTRUCTIONS (340 INSTRUCTIONS)
Table 1 Item Mnemonic Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction.
# ~
RG B
Operation LH
AH
I S T N Z V C RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
101
To Top / Lineup / Index
MB90650A Series
Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL:AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address
AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b
(Continued)
102
To Top / Lineup / Index
MB90650A Series
(Continued)
Symbol rel ear eam rlst Branch specification relative to PC Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension * Meaning
--
@RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16
Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1
Register indirect with 16-bit displacement
2 0 0 2 2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
Note: The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions.
103
To Top / Lineup / Index
MB90650A Series
Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing Listed in tables of instructions 1 2 1 1 2 2 0 0
00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
Note: "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles (b) byte Operand Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits)
Number of cycles Number of access
(c) word
Number of cycles Number of access
(d) long
Number of cycles Number of access
+0 +0 +0 +1 +1 +1
1 1 1 1 1 1
+0 +0 +2 +1 +4 +4
1 1 2 1 2 2
+0 +0 +4 +2 +8 +8
2 2 4 2 4 4
Notes: * "(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Internal memory External data bus (16 bits) External data bus (8 bits) Byte boundary -- -- +3 Word boundary +2 +3 --
Notes: * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. * Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations.
104
To Top / Lineup / Index
MB90650A Series
Table 7 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 # ~ Transfer Instructions (Byte) [41 Instructions]
RG
B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b)
Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) +disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam)
LH AH
I
S
T
N
Z
V
C RMW
2 3 3 4 1 2 2 2 2+ 3+ (a) 2 3 2 2 2 3 3 10 1 1
0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0
Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X - - - - - - - - - - - - - - - - - Z Z - -
* * * * * * * - * * * * * * * * * - * * - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-* -* -* -* -* -* -* -* -* -R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
A, dir 2 3 A, addr16 3 4 A, Ri 2 2 A, ear 2 2 A, eam 2+ 3+ (a) A, io 2 3 A, #imm8 2 2 A, @A 2 3 A,@RWi+disp8 2 5 A, @RLi+disp8 3 10 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH A, ear A, eam Ri, ear Ri, eam 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3
2 4 2+ 5+ (a) 2 7 2+ 9+ (a)
2 0 0 2x (b) 4 0 2 2x (b)
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
105
To Top / Lineup / Index
MB90650A Series
Table 8 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 dir, A addr16, A SP A , RWi, A ear, A eam, A io, A @RWi+disp8, A @RLi+disp8, A RWi, ear RWi, eam ear, RWi eam, RWi RWi, #imm16 io, #imm16 ear, #imm16 eam, #imm16 # Transfer Instructions (Word/Long Word) [38 Instructions] ~
RG
B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c)
Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16
LH AH
I
S
T
N
Z
V
C RMW
2 3 3 4 1 1 1 2 2 2 2+ 3+ (a) 2 3 2 3 3 2 2 5 3 10 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3
0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0
- - - - - - - - - word (A) ((RWi) +disp8) - word (A) ((RLi) +disp8) - word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) - - - - - - - word ((RWi) +disp8) (A) - word ((RLi) +disp8) (A) - word (RWi) (ear) - word (RWi) (eam) - word (ear) (RWi) - word (eam) (RWi) - word (RWi) imm16 - word (io) imm16 - word (ear) imm16 - word (eam) imm16 - word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) long (A) (ear) long (A) (eam) long (A) imm32 long (ear) (A) long (eam) (A) - - - - - - - - - -
* * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVW @AL, AH XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam
2 4 2+ 5+ (a) 2 7 2+ 9+ (a)
2 0 0 2x (c) 4 0 2 2x (c) 0 (d) 0 0 (d)
MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A
2 4 2 2+ 5+ (a) 0 5 3 0 2 4 2 2+ 5+ (a) 0
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
106
To Top / Lineup / Index
MB90650A Series
Table 9 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ ~ 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a)
RG
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
0 0 byte (A) (A) +imm8 0 (b) byte (A) (A) +(dir) 1 0 byte (A) (A) +(ear) 0 (b) byte (A) (A) +(eam) 2 0 byte (ear) (ear) + (A) 0 2x (b) byte (eam) (eam) + (A) 0 0 byte (A) (AH) + (AL) + (C) 1 0 byte (A) (A) + (ear) + (C) 0 (b) byte (A) (A) + (eam) + (C) byte (A) (AH) + (AL) + (C) (decimal) 0 0 0 0 byte (A) (A) -imm8 0 (b) byte (A) (A) - (dir) 1 0 byte (A) (A) - (ear) 0 (b) byte (A) (A) - (eam) 2 0 byte (ear) (ear) - (A) 0 2x (b) byte (eam) (eam) - (A) 0 0 byte (A) (AH) - (AL) - (C) 1 0 byte (A) (A) - (ear) - (C) 0 (b) byte (A) (A) - (eam) - (C) byte (A) (AH) - (AL) - (C) (decimal) 0 0 0 0 word (A) (AH) + (AL) 1 0 word (A) (A) +(ear) 0 (c) word (A) (A) +(eam) 0 0 word (A) (A) +imm16 2 0 word (ear) (ear) + (A) 0 2x (c) word (eam) (eam) + (A) 1 0 word (A) (A) + (ear) + (C) 0 (c) word (A) (A) + (eam) + (C) 0 0 word (A) (AH) - (AL) 1 0 word (A) (A) - (ear) 0 (c) word (A) (A) - (eam) 0 0 word (A) (A) -imm16 2 0 word (ear) (ear) - (A) 0 2x (c) word (eam) (eam) - (A) 1 0 word (A) (A) - (ear) - (C) 0 (c) word (A) (A) - (eam) - (C) 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32
Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- - - - - * - - - - - - - - - * - - - - - - - - - * - - - - - - - * - - - - - - - -
ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL
A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
107
To Top / Lineup / Index
MB90650A Series
Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
2 2 2 0 byte (ear) (ear) +1 2+ 5+ (a) 0 2x (b) byte (eam) (eam) +1 2 3 2 0 byte (ear) (ear) -1 2+ 5+ (a) 0 2x (b) byte (eam) (eam) -1 2 3 2 0 word (ear) (ear) +1 2+ 5+ (a) 0 2x (c) word (eam) (eam) +1 2 3 2 0 word (ear) (ear) -1 2+ 5+ (a) 0 2x (c) word (eam) (eam) -1 2 7 4 0 long (ear) (ear) +1 2+ 9+ (a) 0 2x (d) long (eam) (eam) +1 2 7 4 0 long (ear) (ear) -1 2+ 9+ (a) 0 2x (d) long (eam) (eam) -1
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
* * * * * * * * * * * *
* * * * * * * * * * * *
* * * * * * * * * * * *
- - - - - - - - - - - -
- * - * - * - * - * - *
DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 A A, ear A, eam A, #imm16 A, ear A, eam A, #imm32 # Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~
RG
B 0 0 (b) 0 0 0 (c) 0 0 (d) 0
Operation byte (AH) - (AL) byte (A) (ear) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) (ear) word (A) (eam) word (A) imm32
LH AH
I
S
T
N
Z
V
C
RMW
1 1 2 2 2+ 3+ (a) 2 2 1 1 2 2 2+ 3+ (a) 3 2
0 1 0 0 0 1 0 0
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
- - - - - - - - - - -
2 6 2 2+ 7+ (a) 0 5 3 0
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
108
To Top / Lineup / Index
MB90650A Series
Table 12 Mnemonic DIVU DIVU DIVU A A, ear Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 1 2 ~ *
1
RG
B
Operation
Quotient byte (AL) Remainder byte (AH) Quotient byte (A) Remainder byte (ear) Quotient byte (A) Remainder byte (eam) Quotient word (A) Remainder word (ear) Quotient word (A) Remainder word (ear)
LH AH
I
S
T
N
Z
V
C RMW
0 1 0 1 0
0 word (AH) /byte (AL) 0 word (A)/byte (ear)
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * - - - - - -
* * * * * - - - - - -
- - - - - - - - - - -
*2
A, eam 2+ *3 2 *4
*6 word (A)/byte (eam) 0 long (A)/word (ear)
DIVUW A, ear
DIVUW A, eam 2+ *5 MULU MULU MULU A 1 *8 A, ear 2 *9 A, eam 2+ *10
*7 long (A)/word (eam)
0 0 byte (AH) *byte (AL) word (A) 1 0 byte (A) *byte (ear) word (A) 0 (b) byte (A) *byte (eam) word (A) 0 0 word (AH) *word (AL) long (A) 1 0 word (A) *word (ear) long (A) 0 (c) word (A) *word (eam) long (A)
MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13 *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13:
3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 x (b) normally. (c) when the result is zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
109
To Top / Lineup / Index
MB90650A Series
Table 13 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B
Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A)
LH AH
I
S
T
N
Z
V
C
RMW
2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a)
0 0 1 0 0 (b) 2 0 0 2x (b) 0 0 1 0 0 (b) 2 0 0 2x (b) 0 0 1 0 0 (b) 2 0 0 2x (b)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - *
1 2 0 0 byte (A) not (A) 2 3 2 0 byte (ear) not (ear) 2+ 5+ (a) 0 2x (b) byte (eam) not (eam) 0 0 0 0 1 0 0 (c) 2 0 0 2x (c) 0 0 0 0 1 0 0 (c) 2 0 0 2x (c) 0 0 0 0 1 0 0 (c) 2 0 0 2x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A)
A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a)
NOTW A NOTW ear NOTW eam
1 2 0 0 word (A) not (A) 2 3 2 0 word (ear) not (ear) 2+ 5+ (a) 0 2x (c) word (eam) not (eam)
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
110
To Top / Lineup / Index
MB90650A Series
Table 14 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # ~ Logical 2 Instructions (Long Word) [6 Instructions]
RG
B 0 (d) 0 (d) 0 (d)
Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam)
LH AH
I
S
T
N
Z
V
C
RMW
2 6 2 2+ 7+ (a) 0 2 6 2 2+ 7+ (a) 0 2 6 2 2+ 7+ (a) 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
R R R R R R
- - - - - -
- - - - - -
XORL A, ea XORL A, eam
Table 15 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2
Sign Inversion Instructions (Byte/Word) [6 Instructions]
RG
B 0
Operation byte (A) 0 - (A)
LH AH
I
S
T
N
Z
V
C
RMW
0
X - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
* * * * * *
* * * * * *
- - * - - *
2 3 2 0 byte (ear) 0 - (ear) 2+ 5+ (a) 0 2x (b) byte (eam) 0 - (eam) 1 2 0 0 word (A) 0 - (A)
NEGW A NEGW ear NEGW eam
2 3 2 0 word (ear) 0 - (ear) 2+ 5+ (a) 0 2x (c) word (eam) 0 - (eam)
Table 16 Mnemonic NRML A, R0 # 2 ~ *
1
Normalize Instruction (Long Word) [1 Instruction] Operation
LH AH I S T N Z V C RMW
RG 1
B 0
long (A) Shift until first digit is "1" - byte (R0) Current shift count
-
-
-
-
-
*
-
-
-
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
111
To Top / Lineup / Index
MB90650A Series
Table 17 Mnemonic
RORC A ROLC A RORC ear RORC eam ROLC ear ROLC eam ASR LSR LSL A, R0 A, R0 A, R0
Shift Instructions (Byte/Word/Long Word) [18 Instructions] B 0 0 Operation
byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry
byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit) LH AH I S T N Z V C RMW
# 2 2
~ 2 2
RG
0 0
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - * * -
* * * * * * * * *
* * * * * * * * * * * * * * * * * *
- - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * *
- - - * - * - - - - - - - - - - - -
2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 2 2 *1 *1 *1 2 2 2 *1 *1 *1 *2 *2 *2
2 0 0 2x (b) 2 0 0 2x (b) 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
ASRW A 1 LSRW A/SHRW A 1 LSLW A/SHLW A 1 ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRL A, R0 LSRL A, R0 LSLL A, R0
word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit)
word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0)
** *R -* * * - * * - * * * * * *
2 2 2 2 2 2
long (A) Arithmetic right shift (A, R0)
long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0)
*1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
112
To Top / Lineup / Index
MB90650A Series
Table 18 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 ~ * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10
1
Branch 1 Instructions [31 Instructions] B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 LH AH I S T N Z V C RMW
RG
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0
Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@A addr16 @ear @eam @ear *3 @eam *3 addr24 @ear *4 @eam *4 addr16 *5 #vct4 *5 @ear *6
word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2)
1 (c) 0 2x (c) 0 (c) 0 2x (c) 2 2x (c) 0 *2
CALLP @eam *6 CALLP addr24 *7 *1: *2: *3: *4: *5: *6: *7:
2+ 11+ (a) 4 10
0 2x (c)
word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15, (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15, (PCB) (eam) 16 to 23 word (PC) addr0 to 15, (PCB) addr16 to 23
4 when branching, 3 when not branching. (b) + 3 x (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
113
To Top / Lineup / Index
MB90650A Series
Table 19 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE ear, #imm8, rel
9
Branch 2 Instructions [19 Instructions] B 0 0 0 (b) 0 (c) 0 Operation
LH AH I S T N Z V C RMW
#
~ RG
1
3* 4 *1 *2 *3 *4 *3
0 0 1 0 1 0 2
Branch when byte (A) imm8 - Branch when word (A) imm16 - Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16
- - - - - - - - - - - - - - - -
- - - - - - - - - - R R R R * -
- - - - - - - - - - S S S S * -
- - - - - - - - - - - - - - * -
* * * * * * * * * * - - - - * -
* * * * * * * * * * - - - - * -
* * * * * * * * * * - - - - * -
* * * * * * - - - - - - - - * -
- - - - - - - * - * - - - - - -
4 CBNE eam, #imm8, rel* 4+ CWBNE ear, #imm16, rel 5 CWBNE eam, #imm16, rel*9 5+ DBNZ DBNZ ear, rel eam, rel
- - - - - - - - - - - - -
3 *5 3+ *6 3 *5 3+ *6 2 3 4 1 1 2 20 16 17 20 15 6
Branch when byte (ear) = (ear) - 1, and (ear) 0 2 2x (b) Branch when byte (eam) = (eam) - 1, and (eam) 0 2 Branch when word (ear) = (ear) - 1, and (ear) 0 2 2x (c) Branch when word (eam) = (eam) - 1, and (eam) 0 0 0 0 0 0 0 8x (c) 6x (c) 6x (c) 8x (c) 6x (c) (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt 0
DWBNZ ear, rel DWBNZ eam, rel INT INT INTP INT9 RETI LINK #vct8 addr16 addr24
#local8
UNLINK RET *7 RETP *8 *1: *2: *3: *4: *5: *6: *7: *8: *9:
1 1 1
5 4 6
0 0 0
(c) (c) (d)
At constant entry, save old - frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve - old frame pointer from stack. Return from subroutine Return from subroutine - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
5 when branching, 4 when not branching 13 when branching, 12 when not branching 7 + (a) when branching, 6 + (a) when not branching 8 when branching, 7 when not branching 7 when branching, 6 when not branching 8 + (a) when branching, 7 + (a) when not branching Retrieve (word) from stack Retrieve (long word) from stack In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
114
To Top / Lineup / Index
MB90650A Series
Table 20 Mnemonic PUSHW A PUSHW AH PUSHW PS PUSHW rlst POPW POPW POPW POPW JCTX A AH PS rlst @A # 1 1 1 2 1 1 1 2 1 2 2 2 2 Other Control Instructions (Byte/Word/Long Word) [36 Instructions] ~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2
RG
B (c) (c) (c) *4 (c) (c) (c) *4
Operation
word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)), (SP) (SP) +2n
LH AH
I
S
T
N
Z
V
C RMW
0 0 0 *5 0 0 0 *5
- - - - - - - - -
- - - - * - - - - - - - - - - * * - - * - - - - - - - -
- - - - - - * - * * * - - - - - - - - - - - - - - - - -
- - - - - - * - * * * - - - - - - - - - - - - - - - - -
- - - - - - * - * * * - - - - - - - - - - - - - - - - -
- - - - - - * - * * * - - - - - - - - * * - - - - - - -
- - - - - - * - * * * - - - - - - - - * * - - - - - - -
- - - - - - * - * * * - - - - - - - - - - - - - - - - -
- - - - - - * - * * * - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 6x (c) Context switch instruction 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AND CCR, #imm8 OR CCR, #imm8 MOV RP #imm8 , MOV ILM, #imm8
byte (CCR) (CCR) and imm8 - byte (CCR) (CCR) or imm8 - byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) (SP) +ext (imm8) word (SP) (SP) +imm16 byte (A) (brgl) byte (brg2) (A) No operation
Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space
- - - - - - - - Z - - - - - - - -
MOVEA RWi, ear 2 3 MOVEA RWi, eam 2+ 2+ (a) MOVEA A, ear 2 1 MOVEA A, eam 2+ 1+ (a) ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A 2 3 2 2 1 1 1 1 1 1 1 3 3 *1 1 1 1 1 1 1 1 1
Prefix code for no flag change
Prefix code for common register bank
*1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (pop count) + 2 x (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) - 3 x (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count x (c), or push count x (c) *5: Pop count or push count. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
115
To Top / Lineup / Index
MB90650A Series
Table 21 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC BBS BBS BBS dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4
RG
Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b
LH AH I S T N Z V C RMW
0 0 0
Z Z Z - - - - - - - - - - - - - - - - - -
* * * - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
* * * * * * - - - - - - - - - - - - - - -
* * * * * * - - - - - - * * * * * * * - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - * * * * * * * * * - - - - - - * - -
0 2x (b) bit (dir:bp) b (A) 0 2x (b) bit (addr16:bp) b (A) 0 2x (b) bit (io:bp) b (A) 0 2x (b) bit (dir:bp) b 1 0 2x (b) bit (addr16:bp) b 1 0 2x (b) bit (io:bp) b 1 0 2x (b) bit (dir:bp) b 0 0 2x (b) bit (addr16:bp) b 0 0 2x (b) bit (io:bp) b 0 0 0 0 0 0 0 (b) (b) (b) (b) (b) (b) Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1
Branch when (addr16:bp) b = 1, bit = 1
SBBS addr16:bp, rel WBTS io:bp WBTC io:bp *1: *2: *3: *4: *5:
0 2x (b) 0 0 *5 *5
Wait until (io:bp) b = 1 Wait until (io:bp) b = 0
8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
116
To Top / Lineup / Index
MB90650A Series
Table 22 Mnemonic SWAP SWAPW EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # 1 1 1 1 1 1 ~ RG B 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) byte sign extension word sign extension byte zero extension word zero extension
LH AH I S T N Z V C RMW
- - X - Z -
- * - X - Z
- - - - - -
- - - - - -
- - - - - -
- - * * R R
- - * * * *
- - - - - -
- - - - - -
- - - - - -
Table 23 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI # 2 2 2 2 ~ * *2 *1 *1
2
String Instructions [10 Instructions] Operation
LH AH I S T N Z V C RMW
RG B
* *5 *5 *5
5
* *3 *4 *4 *3 *6 *6 *7 *7 *6
3
Byte transfer @AH+ @AL+, counter = RW0 Byte transfer @AH- @AL-, counter = RW0 Byte retrieval (@AH+) - AL, counter = RW0 Byte retrieval (@AH-) - AL, counter = RW0 Byte filling @AH+ AL, counter = RW0 Word transfer @AH+ @AL+, counter = RW0 Word transfer @AH- @AL-, counter = RW0 Word retrieval (@AH+) - AL, counter = RW0 Word retrieval (@AH-) - AL, counter = RW0 Word filling @AH+ AL, counter = RW0
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - * * * - - * * *
- - * * * - - * * *
- - * * - - - * * -
- - * * - - - * * -
- - - - - - - - - -
2 6m +6 *5 *2 *2 *1 *1 *8 *8 *8 *8
MOVSW/MOVSWI 2 MOVSWD 2 SCWEQ/SCWEQI 2 SCWEQD 2 FILSW/FILSWI
2 6m +6 *8
m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7 x n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case *3: (b) x (RW0) + (b) x (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) x n *8: 2 x (RW0) Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
117
To Top / Lineup / Index
MB90650A Series
s ORDERING INFORMATION
Model MB90652APFV MB90653APFV MB90P653APFV MB90654APFV MB90F654APFV MB90652APF MB90653APF MB90P653APF MB90654APF MB90F654APF Package 100-pin plastic LQFP (FPT-100P-M05) Remarks
100-pin plastic QFP (FPT-100P-M06)
118
To Top / Lineup / Index
MB90650A Series
PACKAGE DIMENSIONS
100-pin plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
1.50 -0.10
51
+0.20 +.008
(Mouting height)
14.000.10(.551.004)SQ
.059 -.004
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05 +.002
"A" 0.50(.0197)TYP 0.18 -0.03 .007 -.001
+0.08 +.003
0.40(.016)MAX 0.127 -0.02 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
100-pin plastic QFP (FPT-100P-M06)
80 81
23.900.40(.941.016) 20.000.20(.787.008)
51 50
3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
100 31
17.900.40 (.705.016)
12.35(.486) REF
16.300.40 (.642.016)
"A" LEAD No.
1 30
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX Details of "B" part
0
10
0.800.20 (.031.008)
C
1994 FUJITSU LIMITED F100008-3C-2
Dimensions in mm (inches) 119
To Top / Lineup / Index
MB90650A Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9910 (c) FUJITSU LIMITED Printed in Japan

▲Up To Search▲

Price & Availability of E713607

	To Download E713607 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .